Digital Design_ Principles and Practices, Chegg Solution Manual_parte_218

Prévia do material em texto

Step 1 of 3 6.15DP Refer Figure X6.13 and Table 6.2 in text book. Design: Using the information in Table 6.2 and Figure X6.13, the values of and for 74LS86 are as follows, and Both Low-to-High and High-to-Low transition causes positive transitions and negative transitions on the outputs of each gate. Thus the exact propagation delay from IN to OUT of the circuit is sum of the propagation delays of the first and third gates low to high transition delays and second and fourth gates high to low transition delays or the vice versa summation. Hence the propagation delay from IN to OUT of the circuit in either case is, Thus, the propagation delay from IN to OUT of the circuit is Step 2 of 3 Single worst case delay specification is the maximum of and specifications. So, single worst case delay for each gate is 23 ns. "The worst case delay through a circuit is computed as the sum of the worst case delays through the individual components, independent of the transition direction and other circuit conditions." Since there are four components in Figure X6.13, the worst case delay through the circuit is, Thus, the maximum propagation delay from IN to OUT of the circuit using single worst case delay is Step 3 of 3 On comparison of the results of calculation of maximum propagation delays using the timing information (80 ns) and using the worst case delay of the circuit (92 ns), calculation of propagation delay using the worst case delay is high. Hence the designer keeps the worst case delay at the time of designing.