Digital Design_ Principles and Practices, Chegg Solution Manual_parte_328

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Step 7.37DP The modified program using the table 7-52 is Program: library IEEE; use use use entity Port R STD_LOGIC; inout STD_LOGIC; QN inout end architecture Behavioral of is begin QN nor Q after 10 Q R nor QN: end Step Test bench: library IEEE; use use use USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD TEXTIO ENTITY ARCHITECTURE testbench OF FILE TEXT OPEN WRITE_MODE IS "results COMPONENT SS PORT R QN InOut logic ); END SIGNAL := SIGNAL SIGNAL Q std_logic SIGNAL QN logic SHARED VARIABLE ERROR INTEGER SHARED VARIABLE LINE; BEGIN UUT PORT MAP S Q=>Q, QN QN ); PROCESS BEGIN Current Time 100ns WAIT FOR 100 ns; S Current Time: 300ns WAIT FOR 200 R Current Time: 400ns WAIT FOR 100 ns; S Current Time 800ns WAIT FOR 400 ns; S Current Time: 1100ns WAIT FOR 300 S WAIT FOR 400 IF (TX ERROR 0) THEN STD TEXTIO string'("No errors or STD TEXTIO ASSERT (FALSE REPORT "Simulation successful (not No problems SEVERI TY ELSE Step STD TEXTIO write(TX OUT, STD TEXTIO string'(" errors found in STD TEXTIO TS, ASSERT (FALSE) REPORT "Errors found during simulation" SEVER END END testbench arch; Step The waveform of the above program is as shown in figure 1. Figure The output in the last input transaction is in metastable state