Digital Design_ Principles and Practices, Chegg Solution Manual_parte_261

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Step 1 of 2 6.059E Refer to Table 6-31 from the textbook for the Verilog code of priority encoder. In this, the for loop starts with highest priority input. Write the Verilog code for priority encoder. module input EI_L; input ouput [2:0] A_L; output EO_L, GS_L; reg [7:0] I; reg [2:0] A, A_L; reg EO_L, EO, GS_L, GS; integer j; always @ (EI_L or El or I_L or or A or EO or GS) begin GS_L=~GS; GS=0; begin if else for (j=7; j>=0; j=j-1) if begin EO = 0; = end end end end module Step 2 of 2 The disable statement is used to exit the for loop. The disable statement was not supported in the Xilinx XST software. But disable statement works in Verilog. Therefore, the Verilog program as shown in Table 6-31, searches for the lowest priority whereas if start the for loop with the highest priority input then it checks for the highest priority input.