Digital Design_ Principles and Practices, Chegg Solution Manual_parte_254

Prévia do material em texto

Step 1 of 3 6.052E The 74x148 uses eight active low inputs to 10 where is holding the highest priority, active low address outputs A2 to A0, two low active enables El for input and the EO for output and a low active group select GS. The low active inputs can be made active if we make them pass through the NOT gates before it reaches 74x148 and the low active address outputs must be inverted so that they can indicate the number of highest priority asserted input. The GS acts as the IDLE in 74x148. When no input is asserted A2- A0, then it will be 111 and IDLE will be asserted as shown in Figure 1. 5 EI 74 148 4 I7 I7 6 3 I6 A2 A2 I6 7 2 I5 I5 9 1 I4 A0 I4 A0 13 I3 I3 I2 12 I2 14 GS IDLE 11 Il EO 15 IO 10 Figure 1 Step 2 of 3 The design works as shown in Table 1. Table 1 Inputs Outputs EI Il I2 I3 I4 I5 I6 A2 A1 A0 IDLE EO 1 X X X X X X X X 0 0 0 1 1 0 X X X X X 1 1 1 1 0 1 0 X X X X X 1 0 1 1 0 0 1 0 X X X 1 0 0 1 0 1 0 1 0 X X X 1 0 0 0 1 0 0 0 1 0 X 1 0 0 0 0 0 1 1 0 1 0 X 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 Step 3 of 3 When no input is asserted A2-A0, then it will be 111 and IDLE will be asserted. The high active address outputs indicates the number of the highest priority asserted input as shown in Table 1.