Chegg Solutions for Microelectronic Circuits (Adel S Sedra, Kenneth C Smith) (Z-Library)_parte_1673

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Step 1 of 3 15.012P Refer to Figure P14.1 (a) in the textbook for a pseudo-NMOS logic circuit with resistive load. The propagation delay from low to high transition, 'PLH is the time at which the output reaches half of the supply voltage. The expression for the output voltage for resistive load is, Find the time at which the output reaches half of supply voltage. Observe that the following condition for the output to reach Simplify the expression to get the time at which the output reaches half of supply voltage. Thus, the value of propagation delay from low to high transition, 'PLH for a pseudo-NMOS logic circuit with resistive load is, - Step 2 of 3 Refer to Figure P14.1 (b) in the textbook for the pseudo-NMOS logic circuit with current-source load. Find the time at which the output reaches half of supply voltage. Consider the following condition for the output to reach Consider that the current source is, Substitute the expression of I in the expression of = = Thus, the value of propagation delay from low to high transition, 'PLH for a pseudo-NMOS logic circuit with current-source load is, Step 3 of 3 Find the percentage reduction of propagation from low to high transition, 'PLH when the current source-load is used from the expressions of 'PLH for the both circuits. =1.38x100 =138% Thus, the percentage reduction of propagation from low to high transition, 'PLH when the current source- load is used is, 138%