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Step of 4 4.044E Consider the BUT gate contains 4 inputs and 2 outputs: B1 A2 Z2 B2 Figure 1: BUT gate logic schematic diagram Step 2 of 4 The BUT gate function is symmetric with respect to the A and B inputs. BUT gate function logic is The output Z1 is high, when inputs A1, B1 are high and inputs A2, B2 are not equal to 1. The output Z2 is high, when inputs A2, B2 are high and inputs A1, B1 are not equal to 1. The truth table for the BUT gate function: 000000 000100 001000 001101 010000 010100 011000 011101 100000 100100 101000 101101 110010 110110 111010 111100 Table 1: Truth table of BUT gate Step 3 of 4 The simplified logic expression for the Z1 after applying the Karnaugh's map: The simplified logic expression for the Z2 after applying the Karnaugh's map: Step 4 of 4 The following is the logic diagram BUT gate drawing using the AND-OR gates and inverters: A1 B1 A2 B2 Al' A2' B2' A1B1B2' Z2 A2B2A1' Figure 2: Equivalent AND-OR-INVERTER circuit for BUT gate