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Step of 5 6.044E (a) The inputs and outputs of the circuit are shown in Table 1: Table 1 Input (from top) Output (from top) Z XYZEN4 Y XYZEN4 XYZEN4 EN1 XYZEN4 EN2 XYZEN4 EN3 XYZEN4 EN4 XYZEN4 XYZEN4 ENIEN2EN3 Step of 5 (b) The circuit is a 3 to 8 decoder. In Table 1, the top eight min-terms are decoder's output terms. The last one is enable signal term. If this enable term is HIGH, the decoder circuit will be in disabled state. Step of 5 (c) The logic symbol is shown in Figure 1: LOGIC SYMBOL Y0 ENI Y1 EN2 Y2 EN3 Y3 EN4 Y4 Y5 Z Y6 Y Y7 Y8 Figure 1 Step of 5 (d) Write the VHDL program as follows: Library IEEE; use IEEE.std_logic_1164.all; entity 3x8 is port (EN1,EN2,EN3,EN4: in STD_LOGIC; enable inputs X,Y,Z in STD_LOGIC select inputs Y: out STD_LOGIC_VECTOR (0 to 7)); - decoded outputs end 3x8; architecture 3x8_a of 3x8 is signal Y_i: STD_LOGIC_VECTOR( 0 to 7); begin with XYZEN4 select Y_i