Atraso de Propagação em Circuitos

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Step 1 of 4 6.11DP Refer Figure X6.9 and Table 6.2 in text book. Design: Replace 74LS00 gates in the Figure X6.9 with 74LS21, draw the modified circuit of Figure X6.9: 1 1 1 U2 OUT 1 U2 1 1 U1 U1 74LS21 U1 74LS21 74LS21 IN 74LS21 74LS21 74LS21 Figure 1 Step 2 of 4 Using the information in Table 6.2 and Figure X6.9, the values of and for 74LS21 are as follows, 15 ns and 20 ns For the circuit Figure X6.9, both LOW-to-HIGH and HIGH-to-LOW transitions cause positive transitions on the output of three gates (altemate gates) and negative transitions on the output of other three gates. Hence, the total delay is the same in both the cases and is, =3(15)+3(20) =45+60 =105 ns Thus, the exact propagation delay from IN to OUT of the circuit is 105 ns Step 3 of 4 Single worst case delay specification is the maximum of and specifications. So, single worst case delay for each gate is 20 ns. "The worst case delay through a circuit is computed as the sum of the worst case delays through the individual components, independent of the transition direction and other circuit conditions." There are six components in the Figure X6.9, so the worst case delay through the circuit is, = 20(6) = 120 ns Thus, the maximum propagation delay from IN to OUT of the circuit using single worst case delay is 120 ns - Step 4 of 4 On of the results of the calculation of maximum propagation delays using the timing information (105 ns) and using the worst case delay of the circuit (120 ns), calculation of propagation delay using the worst case delay is high. Hence the designer keeps the worst case delay at the time of designing.