1 (414)

Prévia do material em texto

Step 1 of 2 8.024E When driving TTL from CMOS, the voltage levels are no problem because the CMOS output approximately 4.95 V for HIGH and 0.05 V for a LOW, which is easily interpreted by the TTL gate. But the current levels can be a real concern because CMOS has severe output-current limitations. The following figures show the input/output currents that flow when interfacing CMOS to TTL: The CMOS can't sink the required by the TTL gate (max.) = 0.51mA (max.) = in (max.) = 1.6 mA 0 0 1 1 0 1 CMOS TTL 74HCMOS 74TTL Step 2 of 2 For the HIGH output condition, the CMOS can source a maximum current of 0.51 mA, which is enough to supply the HIGH-level input current to one TTL gate. But for the LOW output condition, the COS can also sink only 0.51 mA, which is not enough for the TTL LOW-level input current Therefore, the CMOS bus holder circuit doesn't work well three state buses with TTL devices attached.