digital_testing

Prévia do material em texto

DesignforTestabilityinDigital
Integratedcircuits
BobStrunz,ColinFlanagan,TimHall
UniversityofLimerick,Ireland
ThiscoursewasdevelopedwithpartfundingfromtheEUundertheCOMETT
program.TheauthorswishtoexpresstheirthankstoCOMETT.
Documentrescuedfromthedepthsofinternet.
• IntroductionandObjectives 
• TestabilityInDigitalSystems 
o Faults
o TestVectorGeneration 
o CombinationalLogicTest 
• FaultModels 
o Stuck-AtFaults 
o Example
o FaultModelsForBasicGates 
� ANDGate 
� ORGate 
� Inverter
� SpecialCircuits 
• TheSensitizedPathMethod 
o Problemswiththe SensitizedPathMethod 
o MakingChoices 
o ReconvergentFan -outPaths 
• RedundancyandUndetectability 
o Example
• TheD -algorithm
o D-Notation
o SingularCover 
o PrimitiveD -CubesofFailure(P.D.C.F.s) 
� Example
� Example
o PropagationD -Cubes
o D-Intersection
� Example
� Examples
• TheFullD -Algorithm
o Example
o D-Drive
o ConsistencyOperation 
o D-Drive
o ConsistencyOperation 
• OtherTestGenerationMethods 
o L.A.S.A.R.
o P.O.D.E.M.
o BooleanDifferences 
• DesignforTestability 
• Ad-HocTechniques 
• StructuredTechniques 
• ScanPaths 
o ScanPathImplementation 
� StanfordScanPathDesign 
� LatchBasedDesigns 
• SelfTest 
o SignatureAnalysis 
� GeneratingSelfTestPatterns 
o BILBO
� TestProcedurewithBILBO's 
IntroductionandObjectives
ThiscourseprovidesanintroductorytextontestabilityofDigital ASICdevices.Theaim
ofthecourseistointroducethestudenttovarioustechniqueswhicharedesignedto
reducetheamountofinputtestpatternsrequiredtoensurethatanacceptablelevelof
faultcoveragehasbeenobtained.
TestabilityInDigitalS ystems
Beingabletodesignaworkablesystemsolutionforagivenproblemisonlyhalfthe
battleunfortunately.Wemustalsobeabletotestthesystemtoadegreewhichensures
thatwecanhaveahighconfidencelevelthatitisfullyfunctional.Thisi sgenerallynota
straightforwardtask,inverysmallscaledigitalsystems,wecantestexhaustively,thatis
tosay,wecanexercisethesystemoveritsfullrangeofoperatingconditions.Inalarger
scalesystem,itisnolongerpossibletodothisand thereforewemustlookatother
strategiestoensurethatthesystemwillbeproperlytested.
Whentestingadigitallogicdevice,weapplyastimulustotheinputsofthedeviceand
checkitsresponsetoestablishthatitisperformingcorrectly.Thein putstimulusis
referredtoasa testpattern .
Ingeneral,weobservetheresponseofthedeviceatitsnormaloutputpins,however,it
maybethatthedeviceisspeciallyconfiguredduringthetest,topermitustoobserve
someinternalnodeswhichgener allywouldnotbeaccessibletotheuser.
Theresponseofthedeviceisevaluatedbycomparingittoanexpectedresponsewhich
maybegeneratedbymeasuringtheresponseofaknowngooddevice,orbysimulation
onthecomputer.
Ifthedeviceundertest (DUT)passesthetest,wecannotsaycategoricallythatitisa
``good''device.
Theonlyconclusionthatwecandrawfromthedevicepassingatest,isthatthedevice
doesnotcontainanyofthefaultsforwhichitwastested.Itisimportanttograspt his
point,adevicemaycontainahugenumberofpotentialfaults,someofwhichmayeven
maskeachotherunderspecifiedoperatingconditions.Thedesignercanonlybesurethat
thedeviceis100%goodifithasbeen100%tested,thisisrarelypossiblein reallife
systems.
Faults
Whattypeoffaultsarewetryingtodetect?Wearestartingwiththeassumptionthat
logically,thesystemperformsitsdesiredfunction,andthatanyfaultsoccuringwillbe
duetoelectricalproblemsassociatedwithoneormo reofitscomponentparts.
Twokeyconceptsareofinteresthere,theseare:
• Controllability
• Observability
Duringthedesignofasystem,thedesignermustensurethatthetestengineershavethe
meanstosetorresetkeynodesinthesystem,thatis, to control them.Equallyas
importantistherequirementthattheresponsetothiscontrolwillbe observable,thatis,
thatwewillbeabletoseeclearlytheeffectsofthetestpatternsapplied.
1. Controllability -Beingabletosetupknowninternalst ates.
2. CombinatorialTestability -Beingabletogenerateallstatestofullyexerciseall
combinationsofcircuitstates.
3. Observability -Beingabletoobservetheeffectsofastatechangeasitoccurs
(preferablyatthesystemprimaryoutputs).
TestV ectorGeneration
InVLSIcircuits,wehaveahighratiooflogicgatestopinsonthedevice,thereis
generallynowayofaccessingmostofthelogic,sowecannotdirectlyprobetheinternals
ofthedevice.Becauseofthisproblem,weneedawayofgener atingtestswhich,when
appliedtotheinputsofacircuit,giveasetofsignalswhichindicatewhetherornotthe
deviceisgoodorfaulty.Thesetofstimulusinputandexpectedoutputpatterniscalleda
``TestVector''.Thetestvectorsdistinguishbe tweenthegoodmachineandthefaulted
machine.Figure1showsadigitaldevice,aswecansee,thereisonlyaccesstothe
primaryinputsandoutputs,andthereforethedevicemustbetestedusingonlythese
ports.
CombinationalLogicTest
Ifthecombinationallogicblockcontainsnoredundantlogic,
thenthedevicemaybetestedbyapplyingallpossible2^Npossibleinpu tpatterns,Where
Nisthenumberofinputs.Thisistermed``ExhaustiveTesting'',andissatisfactoryfor
smallcircuitsbutrapidlybecomesunweildyasthenumberofinputsgrows.Assuminga
testercapableofapplyingatestpatternevery100ns.Thenwe cancalculatethetesttime
asshownintable1.
Lookingattable1,itisapparantthattheexhaustiveteststrate gygetscompletelyoutof
handquitequickly,andthereforeitisonlyofusewherethereareaverysmallnumberof
inputs.Thisisalsoaveryinefficientteststrategy,mostofthetestpatternsareactually
redundant.Weneedamethodofdeterminingwh ichtestpatternsaresignificant,inorder
toobtainaminimumsetofpatterns.
Variousmethodsarelisted:
1. SensitisedPathMethod.
2. D-Algorithm.
3. CriticalPath(L.A.S.A.R)
4. P.O.D.E.M
5. BooleanDifferences
Currently,the D-Algorithm anditsdescendents, P.O.D.E.Mand L.A.S.A.R arethemost
widelyusedmethods.
FaultModels
AFaultModelisadescription,atthedigitallogiclevel,oftheeffectsofsomefaultor
combinationoffaultsintheunderlyingcircuitry.Theuseoffaultmodelshassome
advantagesandalsosomedisadvantages.
• Advantages
o Technologyindependant.
o Worksquitewellinpractice.
• Disadvantages
o Mayfailtoidentifycertainprocessspecificfaults,forinstanceCMOS
floatinggates.
o Detectsstaticfaultsonly.
Stuck –atfaults:
Example
SingleFault.
ConsideranN -InputANDgate.FortheSTUCK -ATfaultmodel,thereare3^(N+1) -1
differentcasesofsingleandmultiplefaults,withthesinglefaultassumption,thereare
only2(N+1)stuckatfaults.
ANDGate
FortheANDgate,anyinputSA0hasthesameeffectastheoutputSA0.
OutputSA0issaidto COVERalloftheinputS A0faults.Similarly,anyinputSA1
COVERSthefaultoutputSA1.
Thismeansthat:
1. NoInputSA0faultsneedbeincludedinthefaultmodel.
2. TheOutputSA1faultneednotbecoveredeither.
So,theANDgatefaultmodelhasN+1faults,thesearelistedi ntable2
Therefore,withN+1faults,N+1testvectorscancompletelytestanNinputANDgate.
TheN+1faultsCOVERallthe2(N+1)singleSAfaults.Itcanbeshownthattheycover
all3^(N+1) -1multipleSAfaultsaswell.
ORGate
WithanORgate,the OutputSA1coversallInputSA1faults.AnyInputcoversOutput
SA0.Thisisshownintable3.
Inverter
Foraninve rter,theOutputSA1coversInputSA0andtheInputSA0coversOutputSA1.
Thisisshownintable4
SpecialCircuits
Somespecialcircuitscaneasilyhavetestvectorsetsgeneratedforthemwhichmodel
bothsingleandmultiplefaults.Mostsuchcircuitsaregenerallytrivial,however,the2
inputAND -ORcircuitisonewhichisofconsiderablepracticalvalue,itisver ycommon
inPLAstructures.
Suchacircuitisshowninfigure4.
Thecircuitoffigure4realisestheBooleanfuncti on:
Everyproducttermina2levelAND -ORcircuitisaprimeimplicantofthefunction
realisedbythecircuit.Thesepr imeimplicantsmaybeexpressedusingtheCUBE
notation,whichissimplyanalternativewayofexpressinglogicfunctions(thecubes
representtheverticesofahypercubeinaBooleanstatespace).
Sothefunctionmayalsoberealisedas:
Z={(0x0x),(xx01),(11x1),(x110)}
Considernow,thesetoffaults{(1/1),(2/1),(11/0)}
ThiscompletelycoversallotherfaultsinGa teG1.If(11/0)occurs,thecube{(0x0x)}
disappearscompletelyfromZleavingZ'={(x0x1),(1x11),(x110)}AtestvectorforthisfaultisanyinputpatternwhichcausesthetwofunctionsZandZ'to
differ.Sincethe0 -cubes(minterms)ofZ'mustbeas ubsetofthoseinZ,atestvectorfor
11/0wilbeany0 -cubeinZandnotinZ'.
• T(11/0)={Z} -{Z'}
• ={(0000),(0001),(0010),(0011)} -{(x0x1),(1x11),(x110)}
• ={(0000),(0010)}
Ingeneral,foranyAND -gate'soutputSA0,thetestsetmaybefoundbyta kingthe
differencebetweenthedroppedmintermsandtheotherminterms.Thisismosteasily
donebyexpandingthedroppedprimeimplicantstomintermsandcomparingthemwith
theotherpromeimplicants.
TestingANDgateoutputSA0alsotestsfortheappr opriateORgateoutputSA0andany
inverteroutputSA0aswell.
ThetestsetsfortheotherANDgateoutputsSA0are:
• T(12/0)={(1001)}
• T(13/0)={(1111)}
• T(14/0)={(0110),(1110)}
TestingforANDgateinputsSA1
Consider1/1.ThismodifiesZto
Z''={(x0xx),(x0x1),(x110)}
Asbefore,thesetoftestvectorsforthisfaultwillbeallthosemintermsinZandnotin
Z''andviceversa,i.e.,thesetdifference.
• T(1/1)={Z} -{Z''}
• ={(00xx),(x0x1),(1x11),(x110)} -{(x0xx),(x0x1),(1x11),(x110)}
• = {(10xx)} -{(x0x1),(1x11),(x110)}
Expand{(1x0x)}tomintermsandtakethesetdifference
={(1000),(1010)}
Similarly,thetestsetsforsomeoftheotherANDgateinputsSA1are
• T(2/1)={(0110),(0101),(0111)}
• T(3/1)={(0101),(0111),(1101)}
Noticethat thevectors(0101)and(0111)serveastestsforboth2/1and3/1.
TestinganANDgateinputSA1alsotestsfortheORgateoutputSA1,andanyinverter
outputSA1whichliesinthepathtotheANDgateinput.TestingtheANDgateoutput
SA1andeachinp utSA0coverstheANDgate.However,italsocoversboththeORgate
andtheinverters.Thus,bytestingonlytheANDgateweperformacompletetestforall
thefaultsinthecircuit.
TheSensitizedPathMethod
Thisisaheuristicapproachtogenerating testsforgeneralcombinationallogicnetworks.
Thecircuitisassumedtohaveonlyasinglefaultinit.
Thesensitizedpathmethodconsistsoftwoparts
1. ThecreationofaSENSITIZEDPATHfromthefaulttotheprimaryoutput.
2. TheJUSTIFICATION(orCON SISTENCY)operation,wheretheassignments
madetogateinputsonthesensitizedpatharetracedbacktotheprimaryinputs.
Figure5isanexamplenetworkwithanassumedfault7/0.Thesensitizedpathmethod
willbeusedtogenerateatestforthisfault.
PART1 .Createthesensitizedpath.Thisisdonebyforcingthecomplementofthefault
online7andpropagating thisvaluetotheoutput.
Step1 -Createconditionsforfaulttobedetectedonline7,thiscanbeachievedby
applyingthetestvectorforanANDgateoutputSA0 -net1=1andnet2=1.Thevalue
shownonnet7inthetableisthatwhichitwouldcarryintheabsenceofafault.
Step2 -WeneedtopropagatethefaultthroughG5,thismaybedonebysettingnet1 0=
0.
Step3 -WenowneedtopropagatethroughG7,thiscanbeachievedbysettingnet14=
1.
Ingeneralthefaultsignalispropagatedthrougheachgatebypickingacombinationof
theotherinputswhichcausetheoutputtobesolelydependentonthe faultyinput.
Thesensitizationstageisnowcompletebecausethefaulthasbeenpropagatedtoa
primaryinput
PART2 .Justifytheassignmentofvaluestotheoutputsofinternalgatesmadeinpart1
byworkingbackwardstowardstheprimaryinputs.
Interiornets10and14havehadvaluesassignedtothem,correspondingtotheoutputsof
gatesG6andG2.
Firstwenoticethatnet10havingavalueappliedtoitimpliesthevaluesofnets8,11and
12,sotheseareupdatedinstep4.
Step5 -Nowwetrytojustifytheassignmentofalogic1tonet14(outputofG6).Notice
thatnet12=1willforcenet14=1,sothi sconditionisautomaticallyjustified.
Therefore,assignanX(dontcare)tonet9.
Injustifyingnets8and9we havecreatedtwonewgatestojustify,i.e.,G2andG3.
Step6 -G3iseasytojustify,sinceitisXnets5and6canalsobeX.
Step7 -G2maybejustifiedbyeithernet3=0andnet4=Xornet3=Xandnet4=0,
sofinallywehave.
Thetestgenerationisnowfinishedbecausealltheprimaryinputshavebeenassigned
values.T(7/0)={(110XXX),(11X0XX)}.
ProblemswiththeSensitizedPathMethod
1. MakingChoices
2. ReconvergentFan -outPaths.
MakingChoices
Thesensitizedpath methodattemptstodriveatesttoasingleoutput.Whenthe
propagationroutinereachesanetwithfan -outitarbitrarilyselectsonepath.Sometimes
thisblindchoiceofapathignoreseasysolutions.
TheNANDgateG4offigure5iseasytocontrol,itsinputfromG2canbesetto1by
settingPIX5to0.ThismakesaneasypathtopropagatefaultsonG1andothertoi tsleft
toaprimaryoutput.
Ontheotherhand,gateG3willbemoredifficulttocontrolbecauseitsinput(net1)
comesfromotherlogicnotdirectlyconnectedtoaprimaryinput.Moreover,anytest
propagatingthroughG3mustalsopropagatethroughoth erlogic.
ThepaththroughG4istheobviouschoice,butthesensitizedpathheuristichasnowayof
recognizingthisandisjustaslikelytochooseapaththroughG3.
BypreprocessingusingtheSCOAPalgorithm,ahierarchyofsuitablechoicescanbe
established.
ReconvergentFan -outPaths
ThesensitivepathmethodisNOTguaranteedtofindatestforafault,evenwheresucha
testdoesexist.Theprinciplecauseofthisproblemisthepresenceofreconvergentfan -
outpathsinacircuit.
Considerthe circuitoffigure6withfault6/0.Thepathsensitizationprocedureis:
Step1 -Createconditionstodetectfaultonnet6.
Step2 -TrypropagatingthroughgateG5byassigning0tonet1.
Step3 -Nets1and3areboth0fromsteps1and2,=>net5 =1.
Step4 -Nets5=1fromstep4,=>net8=0.
Step5 -Nowpropagatenet9totheoutputbysettingnets8,10,11=0
Thepathsensitizationisnowcompleteasthefaulthasbeenpropagatedtoaprimary
output.Assignmentst ointernalgateoutputsmustnowbejustified.
G6=0andG7=0needtobejustified.StartwithG6=0.
Step6 -Net6isSA0,sonet4=1willjustifynet10=0.
Step7 -ThisimpliesG3=0,fromnet2=0andnownet4=1.
However,thisassignmentisINCONSISTENTbecausenet3=0andnet7=0butalso
net11=0accordingtothetable.Thisisnotcorrect, asthevaluesspecifiedonnets3and
7shouldresultinnet11adoptinga1.Thejustificationprocedurehasfailed.
Onexaminationwecanseethattheproblemarosebecauseweassigneda1tonet4.
However,thisisaninevitableassignmentgiventhep athwearetryingtosensitize.
WecouldbacktrackandtrytosensitizeapaththroughG6,butthesameproblemwould
arise.Itappearsthatthereisnotestfor6/0.However,suchatestdoesexist,itisT(6/0)=
{(0000)}.
Whydoesthesensitizedpath methodfailtofindthistest?
Ifweexamine(0000)weseethatthisvectorsensitizesapaththroughbothG5andG6
simultaneously.Theproblemwiththesensitizedpathmethodisthatitonlyeverattempts
tosensitizeaSINGLEpath.Forreconvergentfa n-outnetworksthiswillusuallycause
problemsduringthejustificationstage.
Theproblemarisesbecause,havingcompletedthesensitization,wemust,during
justification,tracebackalongthealternativepath(s)tothepositionwiththefault.This
willrequireustojustifyagateoneofwhoseinputsisfaulty,whichseverelyrestrictsour
choiceofinputs.Usuallythisleadstothetypeofdifficultiesencounteredinthisexample.
RedundancyandUndetectability
Ifnotestvectorexistsforafaultt henthatfaultisUNDETECTABLE.Undetectable
faultsareusuallycausedbyredundantlogicinacircuit,usuallygatesinsertedtoremove
hazardconditions.
Figure7isanexampleofacircuitcontainingredundantlogicwhichhasanundetectable
fault.
Fault3/1isundetectablebecauseinordertopropagateittonet6werequireX1=1and
X2=1butX1ANDX2=0.
Areundetectablefaultsaproblem?Yes,becausetheycanMASKotherfaults.
Example
FaultMasking.
(110)isatestfor1/0.However,if3/1issimultaneouslypresentinthecircuit,thistest
willfail.
UndetectablefaultsarisefromREDUNDANTlogic.Cons idertheequationofthecircuit
shownabove,
Y=X1ANDX2.Satisfyyourselfthatthisisso.
TheD -algorithm
TheD -algorithmisamodificationofthesensitizedpathmethod.Unlikethelatteritis
guaranteedtofindatestvectorforafaultifonee xists.
TheD -algorithmhasbeenspecifiedveryformally,andissuitableforcomputer
implementation.Itisthemostwidelyusedtestvectorgenerator.
TheprimarydifferencebetweentheD -algorithmandthesensitizedpathapproachisthat
theD -algorithmalwaysattemptstosensitizeeverypossiblepathtotheprimaryoutputs.
• D-Notation
• SingularCover 
• PrimitiveD -CubesofFailure(P.D.C.F.s) 
o Example
o Example
• PropagationD -Cubes
• D-Intersection
o Example
o Examples
D-Notation
Thisisacompactwayofspecifyinghowfaultspropagatethroughacircuit.Disacompositesignal,itimpliesthatinthegoodmachinea1istobefoundatthenode
holdingD,whereasinthefaultedmachi nea0istobefoundatthatnode.Not(D)is
analogouslydefined.
``D''standsfor``discrepancysignal''.
SingularCover
TheSingularCoverofalogicgateisacompactrepresentationofitstruthtable.i.e.,2 -
inputANDgate.
EachrowofthesingularcoveriscalledaCUBE.Thesetofcubeswhichcontain0asthe
outputvalueiscalledtheP0set.Thesetofcubescontaining1astheoutputvalueiscalled
theP1set.FortheANDgate:
AnotherwayofthinkingofthesingularcoverofafunctionF -itistheunionoftheprime
implicantsofFandthoseofNot(F).
PrimitiveD -CubesofFailure(P .D.C.F.s)
APrimitiveD -CubeofFailureforafaultinacircuitisasetofinputstothecircuitwhich
bringthefaulttothecircuitoutput..
TogeneratetheP.D.C.F.forafault
• Generatesingularcoversforthecircuitinbothitsfaultedandfault -freestates.
• IntersecttheP0cubesofthefaultfreecoverwiththeF1cubesofthefaulted
coverandintersecttheP1cubeswiththeF0cubes.
F1andF0playanalogousrolesinthefaultedcovertoP1andP0inthefault -freecover.
Intersectionisdef inedbyintersectingeachelementofthecubesaccordingtothe
followingtable.
Note -DandNot(D)areonlyallow edon OUTPUTpinsforP.D.C.F.
intersection.
 Example
FormtheP.D.C.F.sfora2 -inputANDgatewhereinput1isSA0.
Wealreadyhavethesingularcoverforthefault -freeANDgate,itis
ForthefaultedANDgate1/0thecoveris
i.e.,F1istheemptysetandF0containsallinputcombinations
Now,performingtheintersections
SotheonlyP.D.C.F.for1/0is{(11D)}.
Example
FormtheP.D.C.F.sfora2 -inputANDgatewhereinput2isSA1.
ForthefaultedANDgate2/1 thecoveris:
Intersecting
TheonlyP.D.C.F.for2/1is{(10Not(D))}
PropagationD -Cubes
ThepropagationD -Cubesofagatearethosewhichcausetheoutputofagatetodepend
solelyononeormoreofitsinputs(usuallyone).Thisa llowsafaultonthisinputtobe
propagatedthroughthegate.
ThepropagationD -cubesfora2 -inputANDgateare
TogeneratethepropagationD -cubes,intersectregionP0ofagate'scoverwithregionP1
accordingtothefollowingtable
Ingeneralitispossibletohaveupto2^(2N -1)propagationD -cubesforanN -inputgate,
sonormallyonlythosecubeswithasingleDintheinputsarestored.Cubeswithinthe
inputsareeasilyformedbycomplementingalltheinacube,andcube swithmorethan
oneDintheinputscanbeformedbyintersectingthecovers.
D-Intersection
TheD -Intersectionisthemethodusedtobuildsensitizedpaths.Itisasetofruleswhich
showhowDsignalsattheoutputsofgatesintersectwiththepropaga tionD -cubesof
othergates,allowingasensitizedpathtobeconstructed.
Example
Generateatestfor2/0inthecircuitoffigure8
2/0hasP.D.C.F.{(01Not(D))}.TotransmittheNot(D)onnet4throughG2wemusttry
tomatch(i.e.,intersect)thespecificationwithoneofthepropagationD -cubesforG2.
SuchamatchispossibleifthepropagationD -cube(0DNot(D)) isused.
Examples
ForpurposesofintersectionblankentriesinatablecorrespondtoX's.
TheFull D -Algorithm
1. ChooseaP.D.C.F.forthefaultunderconsideration.
2. Sensitizeallpossiblepathsfromthefaultygatetoaprimaryoutputofthecircuit.
WedothisbysuccessivelyintersectingtheP.D.C.F.ofthefaultwiththe
propagationD -cubesofsucce ssorgates.Theprocessiscalledthe``D -Drive''.
3. JustifythenetassignmentsmadeduringtheD -drivebyintersectingthesingular
coversofgatesinthejustificationpathwiththeexpandingD -cube.Thisiscalled
the``ConsistencyOperation''.
Example
UsetheD -algorithmtogenerateatestfor6/0inthenetworkshowninfigure9.
D-Drive
Step1 -SelectP.D.C.F. for6/0.
Step2 -IntersectwithpropagationD -cubeforNORgateG4.
Step3 -IntersectwithpropagationD -cubeforNANDgateG5.
Atthisstageaprimaryoutputhasbeenreached,sotheD -driveiscomplete
ConsistencyOperation
Step4 -JustifytheassignmentG3=1.ByexaminingthecoverforaNANDgatewesee
that(0X1)willserve.
Step5 -Justifytheassignmen tG1=X.Anycombinationofinputswillserve,sowe
choose(001)arbitrarily.
Allprimaryinputshavebeenassignedvalues,sotheconsistencyoperationiscomplete
andwehaveatestfor6/0.
Thisisaneasyexamplebecausenoinconsistencieswereenc ountered.Whentheyare,it
isnecessarytobacktracktothelastpointatwhichanarbitrarydecisionwasmadeand
makeanotherchoiceatthatpoint.ThiscanleadtoalotofBACKTRACKINGandcan
makethealgorithmveryslowifalotofalternativepaths mustbeexamined.
Figure10isanexamplecircuitwhereinconsistenciesforcebacktracking.
D-Drive
Step1 -Select P.D.C.F.for5/1.
Step2 -Carryoutimplicationsofthischoice,net4becomes1.
Step3 -PropagatethroughG4byusingoneofthepropagationD -cubesoftheNAND
gate.
Step4 -PropagatethroughG5byusingapropagationD -cubeoftheNORgate.
Step5 -WenowhaveDonnet7andNot(D)onnet8.NopropagationD -cubeexistsfor
thiscombinationofinputsonanA NDgate(G6),soNullsareenteredinstead.
Thiscausestheintersectiontofail,sotheD -drivehasfailed.Weneedtobackupand
chooseanothervalueforeithernet7ornet8.ThisisajustificationstepforG6.
Step6 -Wearbitrarilychoosetomod ifynet8andselecttosetitto0.Thisaction
invalidatesanyinputsdrivingG5whichmayhavebeenchosenduringtheD -drive.In
thisinstancethevalueonnet6becomesinvalidandisdropped.
Step6alsofailsbecauseofthelackofapropagationD -cube.Againwemustbackupand
tryanotherchoiceofinput.
Step7 -Thistimewetrynet8=1.ApropagationD -cubedoesexistforthiscombination
ofinputsonG6,sotheintersectionissuccessful.ThiscompletestheD -drive.
ConsistencyOperation
Ifagatehasalogicvalueassignedtoitsoutputbutismissingvaluesatitsinputsitmust
bejustified.GatesG5andG3needjustification.
Step8 -JustifyG5.Thisgatehasafaultononeinput,whichcanbematchedusingan X.
Step9 -JustifyG3.Thiscompletestheconsistencyoperation.
OtherTestGenerationMethods
Inthissection, wewillbrieflyexaminesomeothertestgenerationmethods.
L.A.S.A.R.
L.A.S.A.R. -LogicAutomatedStimulusAndResponse.OtherwiseknownastheCritical
Pathmethod.Unusualinthatallcircuitstobeanalyzedusingthistechniquemustfirstbe
convertedtoNANDequivalentform.VerysimilartothejustificationpartoftheD -
algorithm.Itworksbackfromassumedvaluesonprimaryoutputstowardstheinputs.
UsedintheHILOsimulator.
P.O.D.E.M.
Path-OrientedDEcisionMaking.Thisalgorithmwasdesig nedtogeneratetestsforerror
detection/correctioncircuits.ThesecircuitstypicallycontainlargenumbersofXORgates
whichslowdowntheD -algorithm.Hasbeenfoundtoworkaswellasorbetterthanthe
D-algorithmformostgeneralcircuits.Worksfr omprimaryinputstowardsfaultsiteand
primaryoutputs.
BooleanDifferences
Thisapproachwaspopularamongstresearchersinthe1960's,buthasnotsurvived.
DesignforTestability
Therearevarioustechniquesincommonusagewhichhelpthedesign erofdigitalsystems
toensurethathissystemwillbetestable.Inthefollowingsections,weshallconsider
someofthese.
Ad-HocTechniques
Inthissectionweshalllistasetofwhatmightbetermeddesignfortestabilityrules.
Thesearenotarchite cturedesigntechniquesper -se,butratherasetofguidelines.
1. Aglobalresetsignalisimportant,thisbringsalloftheinternalmemoryelements
toaknownstate.
2. Longcounterchainsshouldbebroken.A10bitcounterneeds1024cyclestotest
itfull y,ifdividedinto25bitcounters,only32cyclesarerequired.(Plusafew
(approx18)cyclesfortestingthedecodelogic.Thisapproachmaybedifficult
withfastsynchronouscounterswithlookaheadcarry.
3. Bringdifficulttotestinternalnodes,out todevicepins.Thismayalsobedifficult,
aspadsareusuallyatapremium.
4. Onboardclockgeneratorsshouldbereplacablebyanexternaltestclocksignal,
thiswillallowexternalcontroloftheclockduringtest.
5. Never,Everuseasynchronousdesign, thiscanleadtoRACEconditions,andlots
ofothernastyproblems.OnlyeverusetheCLEARinputonaflipflopforthe
globalresetsignal.
StructuredTechniques
Figure11illustratesacanonicalmodelofasequentialcircuit.Whatthestructureddesign
fortestabilitytechniquesdo,istobreakthefeedbackpath.Thisallowsaccesstothe
memoryelementsfromexterna lpins.
ScanPaths
SinceIOPinsaregenerallyexpensiveintermsofSiliconarea,andareinshortsupply,
thememoryelements(flipflopsorlatches)areusuallyconnectedinashiftregisterchainfortestpurposes.Thisiscalleda SCANPATH design.
Figure12illustratesthecanonicalsystemoffigure11withaScanPathaddedtoit.
Duringtest,abinarysequencei sshiftedintotheScan_Ininput.Testscanbegeneratedfor
thecombinationallogicblock,bytreatingthememoryelementoutputsasprimaryinputs,
andthememoryelementinputsasprimaryoutputs.
Theshiftregisterchainisfirsttestedbyshiftinga1 0101...patternthroughit,Oncethe
shiftregisterchainhasbeendemonstratedtobeworkingcorrectly,testpatternscanbe
shiftedthroughit.Havingshiftedinatestpattern,thedevicecanbetakenoutofScan
Mode,and1cycleofnormaloperatio nperformed,tocheckthatthecombinationalblock
isworkingwiththatpattern.Thetestresultsmaythenbeshiftedoutinscanmode.
ScanPathImplementation
Scanpathdesignsmaybeimplementedinvariousways
StanfordScanPathDesign
Inthisdesign, thememoryelementsaremadeupofaflip -flop,withanextramultiplexer
addedasshowninfigure13.
Theflip -flopsarethenconnectedasshowninfigure14.
Totestthedesign:
1. Settest=1.
2. Loadtestpatternintoflip -flopsby clocking.
3. Settest=0.
4. Apply1clockpulse,resultsareclockedintothesameflip -flopswhichheldthe
testpattern.
5. Settest=1andclockouttheresult.
LatchBasedDesigns
Latchbaseddesignsattempttoeliminatecircuitracehazards.Acomplete lyhazardfree
circuitiseasiertotestandmorereliable.Themostimportanttechniquewasdevelopedby
IBMandiscalled LevelSensitiveScanDesign orLSSD.
InLSSD,eachmemoryelementconsistsof2latches,theL1latchandtheL2latch.The
L1latc hisa2portlatch,with2clockinputsasshowninfigure15.
InputD1iscontrolledbyclocksignalC1,whenC1is high,thenD1isconnectedtoQ
Normally,D1isconnectedtotheoutputsofthesystemcombinationallogic,andD2to
thescanpath.LatchL2isastandardD -typelatch.Thesystemisconnectedtogetheras
showninfigure16.
ThisisonepossibleLSSDstructure,itisdesignedbydirectlyreplacingflip -flopsinan
IC.EachlatchpairisusedexactlylikeaMaster -Slaveflip -flopinnormaloperation.A2
phase,nonoverlappingclockisusedonCLK1andCLK2asshowninfigure15.
Thet estprocedureisasfollows.
1. ApplypulsestoTSTCLKandCLK2inordertoshiftabitpatternintothecircuit.
2. Apply1CLK1pulsefollowedby1CLK2pulsetorunthetestthroughthecircuit.
3. ClocktheresultoutusingTSTCLKandCLK2.
Thisisonly1t echniquewhichmaybeusedtodesignLSSDcircuits.
SelfTest
VariousformsofselftesttechniquesareusedinmodernDigitalICdesign.Inthe
followingsectionsweshalllookatsomeofthese.
SignatureAnalysis
SignatureAnalysisisadatacompressio ntechnique,ittakesverylongsequencesofbits
fromaunitundertestandcompressesthemintoauniqueN -bitsignaturewhich
representsthecircuit.Agoodcircuitwillhaveauniquesignature,andafaultyonewill
deviatefromthis.
Signatureanalys isisbasedonLinearFeedbackShiftRegisters(LFSR),basically,the
memoryelementsinthesystemarereconfiguredintestmode,toformanLFSR,as
showninfigure18.
Thesummationunit(+)performsmodulo2addition(accordingtotherulesofadditionin
GF(2))ontheincomingbitstreamandthetapscomingbackfromtheLFSR.(XOR
Gates).
Abitstreamisfedinto theregister(whichisinitiallyall0's,becauseyourememberedto
putintheglobalresetsignal!).AfterNclockpulses,theregisterwillcontainthe
signatureofthedatastream.HewlettPackard,amongothers,makesignatureanalysers
forthispurp ose.Suchamachinecantrapall1biterrors,itishoweverpossiblethat2or
moreerrorswillmaskeachother.Theprobabilityoftwodifferentdatastreamsyielding
thesamesignatureisgivenby.
WheremisthelengthoftheLFSRandnisthelengthofthesequence,forntendingto
infinitythistendsto.
Sobymakingmlarge,theprobabilityofabadsequencebeingmaskedissmall.Hewlett
Packardusem=16,givingPerr=1.5E -5andhavenotfoundthiserrorprobabilityto
poseapro bleminpractice.
GeneratingSelfTestPatterns
LFSR'scorrespondingtoprimitivepolynomialsoverGF(2)makegoodsourcesof
pseudo-randompatterns(PRBS).Asanexample,considerfigure19wherethesequence
lengthwillbe2^16 -1distinctpatterns(all zerosisnotallowed).
Toperformin -situtestingofalogicnetwork,wecouldplaceoneoftheseregistersatits
input,andsomesignatureanalysiscircuitryattheoutput.TheLFSRgeneratesrandom
binarysequenceswhicharefedthroughthenetworkundertest,andanalysedbythe
signatureanalysers.
BILBO
BILBO,isaratherunfortunateacronymfor BuiltInLogicB lockObservation ,it
implementsthesignatureanalysisidea,inpractice.Thememoryelementsinthesystem
areconnectedinaScanPathasshowninfigure20.
EachBILBOcanactas.
• AScanPathshiftregister.
• AnLFSRgeneratingrandompatterns.
• Amulti -inputsignatureanalyser.
Providedthatthestartstateisknown,andthataknownnumberofclockcyclesare
injected,thefinishstatewillbeaknownpattern.
TestProcedurewithBILBO's
TestingusingBILBO'siscarriedoutasfollows.
Forlogicblock1.
1. BILBO1isinitialisedtoanon -zeroinitialstatebyshiftinginapatternthrough
Scan_In.
2. BILBO1isconf iguredasaPRBSgeneratorandBILBO2asamulti -input
signatureanalyser.
3. Nclockpulsesareapplied.
4. BILBO2isconfiguredasaScan -Path,andtheresultisshiftedoutthrough
Scan_Out.
Totestlogicblock2,BILBO2becomesthesequencegenerator, andBILBO1the
signatureanalyser.
Thequalityofthetestsgenerated(faultcoverage)mustbedeterminedbypriorfault
simulation.Thefinalsignaturemaybedeterminedbycheckingaknowngoodpart
(Dangerous!)orbylogicsimulation.
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Thetranslationwasinitiatedbystrunzb@itdsrv1.ul.ieonMonJan2316:44:16WET
1995