Resolução cap11-Introdução aos sistemas digitais-Ercegovac

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215
Chapter 11
Exercise 11.1 The register requires the load (LD), clear (CLR), and data inputs that are not
available in the SR 
ip 
op. We need to design a combinational network to generate the correct
SR inputs as shown in the next table:
x LD CLR S R
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 0 0
1 0 1 0 1
1 1 0 1 0
1 1 1 0 1
From the table we obtain:
S = x:LD:CLR
0
R:
0 1 1 1
0 1 1 0
CLR
LD
x
�
�
�
�
�
�
	
R = CLR+ LD:x
0
The circuit for the 4-bit register using SR 
ip 
ops is shown in Figure 11.1.
S
R
Q
LD
x
CK
CLR
M M
M
M
M
x3
x2
x1
x0
CKLD
CLR
q3
q2
q1
q0
Figure 11.1: 4-bit register using SR 
ip 
ops - Exercise 11.1
216 Solutions Manual - Introduction to Digital Design - July 1, 1999
Exercise 11.2: The implementation of a serial-in/parallel-out right/left shift register using
parallel-in/parallel-out right shift register is shown in Figure 11.2.
CK
Ir
Shift Right
Shift Left
Parallel In/out RSR
I L
Q0Q1Q2Q3
Ir
Shift
LOAD
I3 I2 I1 I0
Q3 Q2 Q1 Q0
Figure 11.2: serial-in/parallel-out right/left shift register
The SHIFT input is used to enable the shift-right function, while the serial data is entered
through the I
r
input. The LOAD input is used to shift left, while the serial data and other next
state bits are entered through the parallel inputs of the shift register (I
i
).
Exercise 11.3
Bit-serial arithmetic for addition/subtraction of 16-bit operands in two's complement form. The
network for this exercise is shown in Figure 11.3. The two serial inputs a and b are added/subtracted
generating the result s, from least-signi�cant to most-signi�cant bit. When subtraction is requested,
a carry in of 1 in the �rst clock cycle is applied to the Full-Adder, together with the complementation
of all bits of b. When the 16
th
bit of the number is being computed, the signal last bit is 1. Observe
that the serial hardware may compute a di�erent number of bits only changing the counter design.
Exercise 11.4 The pattern recognizer for the sequences 0101 and 0110 is presented in Fig-
ure 11.4.
Exercise 11.5: (a) Consider the information provided in Table 11.1, which presents the network
operation for the inputs x = 01101001 and y = 00010110:
Observe that a new digit begins when K
0
= 1. There is a delay of 4 cycles between the input
digits and the output digit. The result of the operation is 85 in decimal. It is correct since x = 69
and y = 16.
(b) The output of the �rst serial adder is the radix-2 sum of the x and y bit strings. Consider
a group of four bits corresponding to one decimal digit of x and y. These bits are applied at the
input of the adder from least signi�cant to most signi�cant at clock cycles when K
0
, K
1
, K
2
, and
K
3
are active. Consequently, at the time K
3
is active, the sum is (c
4
; s
3
; s
2
; s
1
; s
0
), as indicated
below:
x
3
x
2
x
1
x
0
+ y
3
y
2
y
1
y
0
c
4
s
3
s
2
s
1
s
0
Bits (s
2
; s
1
; s
0
) are inside the shifter, s
3
and c
4
are outputs of the �rst adder. Since the result
Solutions Manual - Introduction to Digital Design - July 1, 1999 217
FA
D Q
CK
subtract
cincout
Modulo-16
counter
CK
CLR
4
last_bit
b
s
TC
zero
shift reg.
Load
CK
16
1
Shift
shift reg. CK
16
Shift
1
parallel input
parallel output
a
shift reg.
Load
CK
16
1
Shift
parallel input
Figure 11.3: Serial addition - Exercise 11.3
should be in BCD (radix-10) it is necessary to correct it whenever it is larger than 9. That is:
z = s mod 10 =
(
s if s � 9
s� 10 if s � 10
(11:1)
where s = 16c
4
+
P
3
i=0
s
i
2
i
. Consequently, it is necessary to detect whether the addition of 2
decimal digits is greater than 9 and then subtract 10 form the result.
Moreover, the carry to be used for the next digit is
C
out
=
(
1 if s � 10
0 if s � 9
(11:2)
3-bit Shift RegisterCK
x
z
input
Figure 11.4: Pattern recognizer - Exercise 11.4
218 Solutions Manual - Introduction to Digital Design - July 1, 1999
K0 K1 K2 K3 x y S
i
c
i+1
shift reg. FF 2
nd
adder input Internal carry z
(K1 +K2)FF (serial adder)
1 0 0 0 1 0 1 0 0000 0 0 0 0
0 1 0 0 0 1 1 0 1000 0 0 0 0
0 0 1 0 0 1 1 0 1100 0 0 0 0
0 0 0 1 1 0 1 0 1110 0 0 0 0
1 0 0 0 0 1 1 0 1111 1 0 0 1
0 1 0 0 1 0 1 0 1111 1 1 1 0
0 0 1 0 1 0 1 0 1111 1 1 1 1
0 0 0 1 0 0 0 0 1111 1 0 1 0
1 0 0 0 0 0 0 0 0111 0 0 1 0
0 1 0 0 0 0 0 0 0011 0 0 1 0
0 0 1 0 0 0 0 0 0001 0 0 1 0
0 0 0 1 0 0 0 0 0000 0 0 0 1
1 0 0 0 0 0 0 0 0000 0 0 0 0
Table 11.1: Circuit behavior - Exercise 11.5
which can be written as
C
out
=
(
1 if (s � 16) or (10 � s < 16)
0 otherwise
(11:3)
As BCD digits come in groups of 4 bits, the detection of greater or equal to 10 condition as
presented in Equation 11.3 corresponds to the following expression:
G = c
4
+ s
3
(s
2
+ s
1
)
This detection is implemented in the combinational network connected to the outputs of the �rst
adder and the shift register. The value of G is stored in the FF only when K
3
= 1. In any other
cycle the value in the FF doesn't change (function performed by the FF and MUX circuit).
For the subtraction of 10 (when the addition of the two BCD digits are larger than 9), since
binary adders add modulo-16 instead, the following equation must be considered:
s� 10 = (s+ 6) mod 16
This addition of 6 is performed using the second binary adder. Since the binary representation
of 6 is 0110, it's necessary to add 1 in two consecutive cycles. The least signi�cant bit of the �rst
addition reaches the second adder when K
0
is active, if the addition of 6 is necessary, the input of
the second adder must have a 1 during the cycles when K
1
or K
2
are active.
Note that when the least signi�cant bits of another pair of BCD digits come into the �rst adder,
the least signi�cant bit of the addition of the previous pair is at the input of the second serial adder.
The analysis �nishes when we consider the carry bits of the BCD addition. When the sum
value of the digits of x and y is a value greater than 15, the carry bit is stored in the �rst adder,
to be used with the next BCD digits. When the value is in the range 10 to 15, the correction step
(addition of 6) executed in the second adder generates a carry which is stored in the second adder
for the next sum value which is the contents of the shifter.
Solutions Manual - Introduction to Digital Design - July 1, 1999 219
x
y
si
shift reg
FF out
FF in
CK
z
1000 1100
K3
ci+1
K0
K2
K1
0110 1011 1101 1110 0111 1011 0101 0010 0001 0000 0000
Figure 11.5: Timing diagram for Exercise 11.5
The timing diagram is shown in Figure 11.5.
Exercise 11.6: The state diagram for this sequential network is presented in Figure 11.6, for
the case of receiving least signi�cant bit and most signi�cant bit �rst. In each transition we use a
pair of bits representing the inputs x and y, respectively. The system output corresponds to the
system's present state.
(a) The system implementation for the comparison starting with the least signi�cant bit is
shown in Figure 11.7. A one-hot state encoding is used. The expressions for the next state in this
case are:
E(t+ 1) = E(t):(x = y)
G(t+ 1) = G(t):(x = y) + (x > y)
S(t+ 1) = S(t):(x = y) + (x < y)
The initialize input clears the 
ip-
ops and the counter suchthat initially E = 1, G = S = 0,
and the counter state is 0. The counter monitors the number of clock cycles while the signal compare
is active. After 32 clock cycles the Done signal becomes active for one clock cycle. Load signal
is used to store the parallel input values into the shift register. The system must be reset to start
another operation.
(b) The implementation of the serial comparator starting with the most-signi�cant bit is shown
220 Solutions Manual - Introduction to Digital Design - July 1, 1999
SMALLER
GREATEREQUAL
equal
xi<yi
xi>yi
LEAST SIGNIFICANT BIT FIRST
SMALLER
GREATEREQUAL
equal
MOST SIGNIFICANT BIT FIRST
xi>yi
equal
xi<yi
xi>yi
xi<yi
equal
xi>yi
xi<yi
Figure 11.6: State Diagrams for Serial Binary Magnitude Comparators - Exercise 11.6
x
x>y
x<y
x=y
D Q
D Q
D Q
initialize
CK
G
E
S
CNT
CLR
LD q4 q3 q2 q1 q0
I4 I3 I2 I1 I0
TCMod-32 Counter Done
CK
0
initialize
Compare
Shift Register
CK
Load
y
Shift Register
CK
Load
Figure 11.7: Serial Binary Magnitude Comparator - LS bit �rst - Exercise 11.6
in Figure 11.8. The expressions for the next state in this case are:
E(t+ 1) = E(t):(x = y)
G(t+ 1) = G(t) +E(t):(x > y)
S(t+ 1) = S(t) +E(t):(x < y)
The counter has the same function as the one used in part (a).
Exercise 11.7:
(a) The implementation of the serial change of sign module (complementer) for a 32-bit number
in two's complement system is shown in Figure 11.9. After the clear signal the counter is in state
0 and the NOR gate connected to its output forces a 1 input into the half-adder (HA). The other
input of the HA is connected to the complemented serial output of the shift register. The bits are
shifted out least-signi�cant bit �rst and stored back into the same register. The carry bit of each
bit addition is delayed and inserted back into the HA, as done in serial addition.
(b) When the adder receives two bits each clock cycle, it is necessary to use two shift registers.
One stores the bits of X in even positions, X
even
= (x
30
; x
28
; : : : ; x
2
; x
0
). The other stores the bits
Solutions Manual - Introduction to Digital Design - July 1, 1999 221
x>y
x<y
x=y
D Q
D Q
D Q
initialize
CK
G
E
S
CNT
CLR
LD q4 q3 q2 q1 q0
I4 I3 I2 I1 I0
TCMod-32 Counter Done
CK
0
initialize
Compare
x
Shift Register
CK
Load
y
Shift Register
CK
Load
Figure 11.8: Serial Binary Magnitude Comparator - MS bit �rst - Exercise 11.6
Shift Register
X
32
HA
CNT
CLR
LD q4 q3 q2 q1 q0
I4 I3 I2 I1 I0
TCMod-32 Counter
CK
0
clear
complement
CK
FFCK
In out
Done
Figure 11.9: Serial change of sign (two's complement system) - Exercise 11.7
in odd positions, X
odd
= (x
31
; x
29
; : : : ; x
3
; x
1
). The output is stored back into the registers with
the same organization. Two HAs with extra logic are used to increment X
0
. Since 2 bits per clock
cycle are processed, a modulo-16 counter is enough. This design is shown in Figure 11.10.
Exercise 11.8: The implementation of the variable-length shift register is presented in Fig-
ure 11.11. Since the length of the shift register varies from 1 to 8, we use a 3-bit control variable
represented as L = (L
2
; L
1
; L
0
). The value L = 0 corresponds to the shift of 8 bit positions. L is
used as selection control signal for the multiplexer. The multiplexer selects the proper output of
the shifter that corresponds to the system output for a given value of L. So, for example, if L = 3
then z is obtained from output 2 of the shift register, imposing a delay of 3 clock cycles from the
data input to the output z.
Exercise 11.9: The design is presented in Figure 11.12. A modulo-m divider is implemented
by a counter that loads the value 16 �m every time TC is 1. In two's complement system, the
222 Solutions Manual - Introduction to Digital Design - July 1, 1999
Shift Register
X
16
HA
CK
FFCK
In out
Shift Register
X
16
CK
In out
X
even
odd
HA
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
0
clear
complement Done
32
Figure 11.10: Serial complementer (two's complement system) - Exercise 11.7
computation of 16�m results in �m. The value of �m is obtained from m by bit complementation
(Compl module) and addition of 1. Another option is to use 15 �m as a loading value and load
the counter with this value when it reaches the state 14. Such operation corresponds to the one's
complement of m and it is obtained by simple bit complementation (no incrementer).
Exercise 11.10: The solution for this exercise is shown in Figure 11.13. The network computes
the next state adding one to the present state value when the value is less than 9, or adding 7 to
the present state when it reaches 9 (forcing the counter to go back to state 0). Using high-level
speci�cation we have:
s(t) =
(
s(t) + 1 if s(t) < 9
(s(t) + 7) mod 16 = 0 if s(t) = 9
Serial IN
CK
Data
Input
SHIFT 
REGISTER
0 1 2 3 4 5 6 7
E
2
1
0
MUX 1
z
L2
L1
L0
0 1 2 3 4 5 6 7
Figure 11.11: Variable-length serial-in/serial-out shift register - Exercise 11.8.
Solutions Manual - Introduction to Digital Design - July 1, 1999 223
m
CNT Modulo-16
 counter TC
Compl
Incrementer
LOAD
I2I3 I1 I0
Q2Q3 Q1 Q0 z
CK
1
m
CNT Modulo-16
 counter TC
LOAD
I2I3 I1 I0
Q2Q3 Q1 Q0 z
CK
1
state 14
(a) (b)
Figure 11.12: Programmable modulo-m divider - Exercise 11.9
RegisterCK
Binary ADDER 0
0 1
Figure 11.13: BCD counter - Exercise 11.10
Exercise 11.11: Using a modulo-16 binary counter with parallel inputs
(a) 4-to-11 counter.
CNT = x
LOAD = Q
3
Q
1
Q
0
x = TC
I = 0100
The network is shown in Figure 11.14.
(b) modulo-13 counter.
CNT = x
LOAD = Q
3
Q
2
x = TC
I = 0000
The network for this counter is shown in Figure 11.15.
224 Solutions Manual - Introduction to Digital Design - July 1, 1999
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
clear
0 1 0 0
x
TC
Figure 11.14: 4-to-11 counter - Exercise 11.11(a)
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
clear
0 0 0 0
x
TC
Figure 11.15: Modulo-13 counter - Exercise 11.11(b)
(c) The state diagram is shown in Figure 11.16, with notes associated to the transitions for
which the counter must be loaded. From the diagram we obtain the condition for loading on a
Kmap as follows:
0 0 0 0
0 1
- -
- -
0 0
0 0 1 0
Q
0
Q
1
Q
2
Q
3
�
�
	
�
�
	
that results in the minimal expression:
LOAD = (Q
3
Q
0
2
Q
1
Q
0
+Q
0
3
Q
2
Q
0
)x
Solutions Manual - Introduction to Digital Design - July 1, 1999 225
0 1 2 3 4 5
15 14 11 10 9 8
counter loads
the value
counter loads
the value
Figure 11.16: State diagram for Exercise 11.11(c)
We use the fact that LOAD overides CNT input to de�ne:
CNT = x
Considering the inputs I
i
as d.c.s for the cases when LOAD = 0 and the appropriate next state
value for when LOAD = 1, and using Kmaps we obtain the expressions:
I
3
= 1
I
2
= I
1
= Q
1
I
0
= 0
The network for this system is shown in Figure 11.17.
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
clear
x
Q1 0
Q3
Q2’
Q1
Q0
Q3’
Q2
Q0
LOAD
Q2’
Q3’Q3
Q2
Q1 Q0
1
Figure 11.17: Network for Exercise 11.11(c)226 Solutions Manual - Introduction to Digital Design - July 1, 1999
Exercise 11.12: Actually what was intended in this exercise was to design the counters of Ex.
11.11. However, since there is a typo, we give the solution as stated. The design of a BCD counter
for both cases are given next:
(a) using T type 
ip 
ops and NAND gates. The state transition table is:
PS Input Input
x = 0 x = 1 x = 0 x = 1
0000 0000 0001 0000 0001
0001 0001 0010 0000 0011
0010 0010 0011 0000 0001
0011 0011 0100 0000 0111
0100 0100 0101 0000 0001
0101 0101 0110 0000 0011
0110 0110 0111 0000 0001
0111 0111 1000 0000 1111
1000 1000 1001 0000 0001
1001 1001 0000 0000 1001
NS T
3
T
2
T
1
T
0
From the table we obtain T
0
= x and draw the following Kmaps for the other variables when
x = 1:
T
3
0 0 0 0
0 0 1 0
- - - -
0 1
- -
Q
0
Q
1
Q
2
Q
3
�
�
�
�
�
�
	
T
2
0 0 1 0
0 0 1 0
- - - -
0 0
- -
Q
0
Q
1
Q
2
Q
3
�
�
	
T
1
0 1 1 0
0 1 1 0
- - - -
0 0
- -
Q
0
Q
1
Q
2
Q
3
�
�
�
�
and the minimal expressions are:
T
3
= Q
3
Q
0
x+Q
2
Q
1
Q
0
x
T
2
= Q
1
Q
0
x
T
1
= Q
0
3
Q
0
x
The network of this design is shown in Figure 11.18.
(b) same solution given to Exercise 11.10.
Exercise 11.13:
Assuming that the module-16 counter has only up-counting feature, the down-counting must
be implemented by loading the next state and a zero must be loaded when up-counting and the
counter state (count) is 10.
The LOAD signal is expressed as:
LOAD =
(
1 if (countup and count = 10) or countdown
0 otherwise
The value to be loaded is:
Solutions Manual - Introduction to Digital Design - July 1, 1999 227
T Q
Q’
Q3
Q0
Q2
Q1
Q0
3
Q3
Q3’
T Q
Q’
Q1
Q0 Q2
T Q
Q’
Q0
Q3’ Q1
2
1
T Q
Q’
0
x Q0
x
x
CK
CK
CK
CK
x
Figure 11.18: BCD counter using T 
ip 
ops - Exercise 11.12(a)
i =
8
>
>
>
<
>
>
>
:
i� 1 if countdown and count 6= 0
(10)
10
if countdown and count = 0
0 if countup and count = (10)
10
don't care otherwise
Representing the parallel input i by a vector I = (I
3
; I
2
; I
1
; I
0
) and the count state by a vector
Q = (Q
3
; Q
2
; Q
1
; Q
0
), the following expression is obtained:
LOAD = countup:Q
3
:Q
1
+ countdown
Lets �rst consider the values to be loaded when counting down.
Q = (Q
3
; Q
2
; Q
1
; Q
0
) I = (I
3
; I
2
; I
1
; I
0
)
0000 1010
0001 0000
0010 0001
0011 0010
0100 0011
0101 0100
0110 0101
0111 0110
1000 0111
1001 1000
1010 1001
1011 - - - -
1100 - - - -
1101 - - - -
1110 - - - -
1111 - - - -
228 Solutions Manual - Introduction to Digital Design - July 1, 1999
I
3
:
1 0 0 0
0 0 0 0
- - - -
0 1
-
1
Q
0
Q
1
Q
2
Q
3
�
�
�
�
�
�
�
�
�
�
�
I
2
:
0 0 0 0
0 1 1 1
- - - -
1 0
-
0
Q
0
Q
1
Q
2
Q
3
�
�
�
�
�
�
�
�
�
�
�
I
3
= (Q
0
3
Q
0
2
Q
0
1
Q
0
0
+Q
0
Q
3
+Q
1
Q
3
):countdown
I
2
= (Q
2
Q
0
+Q
2
Q
1
+Q
3
Q
0
1
Q
0
0
):countdown
I
1
:
1 0 1 0
1 0 1 0
- - - -
1 0
-
0
Q
0
Q
1
Q
2
Q
3
�
�
�
�
�
�
I
0
:
0 0 0 1
1 0 0 1
- - - -
1 0
-
1
Q
0
Q
1
Q
2
Q
3
�
�
�
�
�
�
�
�
�
�
�
I
1
= (Q
0
1
Q
0
0
+Q
1
Q
0
):countdown
I
0
= (Q
2
Q
0
0
+Q
3
Q
0
0
+Q
1
Q
0
0
):countdown
Since when countup = 1 we must have countdown = 0, the value loaded when counting up (at
state count = 10) is I = 0, which is correct.
The network that implements the counter is shown in Figure 11.19. Black boxes were used to
represent the gate networks that implement I
3
; I
2
; I
1
; and I
0
.
Exercise 11.14: The state and output are represented by the vector (Q
4
; Q
3
; Q
2
; Q
1
; Q
0
),
where Q
4
is the output of the 
ip-
op, and (Q
3
Q
2
Q
1
Q
0
) is the output of the modulo-16 counter.
To achieve the desired counting sequence it is necessary to have:
LD =
(
1 if (Q
4
; Q
3
; Q
2
; Q
1
; Q
0
) = (25)
10
0 otherwise
Moreover, the additional 
ip-
op is set to 1 when the modulo-16 counter goes from 15 to 0,
which corresponds to the clock cycle when TC = 1, and reset when the state 5 is loaded. The
network is shown in Figure 11.20.
Exercise 11.15:
There is a mistake on Figure 11.32 of the textbook. The two counters should be con�gured as
shown in Figure 11.21.
The �rst counter has a load condition given as
LD = S
0
1
for which the value loaded is I = (S
3
; 1; 1; 0), and z = S
3
. Looking at all possible present states we
are able to obtain the following state-transition and output table:
Solutions Manual - Introduction to Digital Design - July 1, 1999 229
Modulo-16 counter
Q_
Q_
Q3 Q2 Q1 Q0
I3 I2 I1 I0
L
CNT
clrCLEAR
4
4 4 4 4
countdown
CC4 CC3 CC1CC2
where CCi means
combinational circuit 
for function I
LOAD
countdown
Q3
Q1
countup
CK
i
Figure 11.19: Modulo-11 up/down counter - Exercise 11.13
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
clear
x
Q3 Q2 Q1 Q0
J
K
Q
CK
Q4
0 1 0 1
Q4
Q3
Q0
Figure 11.20: Network for Exercise 11.14
PS NS output (z)
0000 0110 0
0110 0111 0
0111 1000 0
1000 1110 1
1110 1111 1
1111 0000 1
This counter implements a modulo-6 frequency divider, with 50%-duty-cycle frequency.
The second counter has LD = S
0
2
, z = S
3
, and I = (S
3
; 1; 0; 0). The state-transition and output
table for this case is:
230 Solutions Manual - Introduction to Digital Design - July 1, 1999
Module-16
Counter
I3 I2 I1 I0 LD
TC
S3 S2 S1 S0 CLR
CNT x
CLK
1 1 0
z
Module-16
Counter
I3 I2 I1 I0 LD
TC
S3 S2 S1 S0 CLR
CNT x
CLK
1 0 0
z
Figure 11.21: Frequency dividers for Exercise 11.15
PS NS z
0000 0100 0
0100 0101 0
0101 0110 0
0110 0111 0
0111 1000 0
1000 1100 1
1100 1101 1
1101 1110 1
1110 1111 1
1111 0000 1
This counter implements a modulo-10 frequency divider, with 50%-duty-cycle frequency.
The timing diagram for both cases is shown in Figure 11.22.
CLK
z
first
counter
z
second
counter
Figure 11.22: Timing digram for counters in Exercise 11.15
Exercise 11.16: The state diagram is presented in Figure 11.23. The condition for LOAD is:
LOAD = S
0
x+ S
1
x+ S
2
x
0
+ S
3
x
0
+ S
4
x+ S
5
x+ S
6
where S
i
is a product term that is 1 when the state is i. The values to be loaded are presented in
the next table:
Solutions Manual - Introduction to Digital Design - July 1, 1999 231
State State code (Q
2
; Q
1
; Q
0
) Inputs (I
2
; I
1
; I
0
)
S
0
000 000
S
1
001 000
S
2
010 001
S
3
011 001
S
4
100 000
S
5
101 000
S
6110 101 when x' and 011 when x
From the table we can use K-maps to get the following expressions. Care must be taken with
the input values for I
j
when in S
6
. In this particular case, LOAD is active independent of x, and
the input is a function of x:
I
2
= Q
2
Q
1
x
0
I
1
= Q
2
Q
1
x
I
0
= Q
1
When the value of the LOAD input is not active, the counter goes to the next state ((s(t) +
1) mod 8). The circuit is presented in Figure 11.23.
0 0 1 1 0
01
1
0
1 1
0
0
1
S6/0S5/1S4/0S3/0S2/0S1/0S0/0
Q1
0
1
2
3
4
5
6
7
2 1 0
MUX
CK
LD
CK
CNT
CLR
Modulo-16
Counter
 Q2 Q1 Q0
I3 I2 I1 I0
Q3 Q2 Q1 Q0
Q2 Q1 Q0
x
x
x’
x’
x
x
1
clear 0
Q1
Q2 x’ Q1
Q2 x
Figure 11.23: Exercise 11.16
232 Solutions Manual - Introduction to Digital Design - July 1, 1999
Exercise 11.17:
From the network in Figure 11.33 of the text we get the following expressions for timing behavior:
z(t+ 1) = [z(t) + COUNT (t)] mod 256
COUNT (t+ 1) = [COUNT (t) + 1] mod 256
with the initial condition COUNT (0) = c
0
we get the solution for the second recurrence as:
COUNT (t) = (t+ c
0
) mod 256
The �rst recurrence equation is transformed to:
z(t+ 1) = [z(t) + ((t+ c
0
) mod 256)] mod 256 = [z(t) + t+ c
0
] mod 256
To �nd a solution for the �rst recurrence, let us evaluate a few terms, considering the initial
condition z(0) = z
0
:
z(1) = (z
0
+ 0 + c
0
) mod 256
z(2) = ((z
0
+ 0 + c
0
) + 1 + c
0
) mod 256 = (z
0
+ 1 + 2c
0
) mod 256
Then the general solution is:
z(t) = (z
0
+
t�1
X
i=0
i+ tc
0
) mod 256 = (z
0
+ (t� 1)t=2 + tc
0
) mod 256
For z
0
= 0 and c
0
= 0 we get:
z(10) = (
9
2
� 10) mod 256 = 45
Exercise 11.18:
To simplify the notation, let us use the following variables:
A = (DIST � 10)AND(COUNT = 3)
B = (DIST > 10)
C = (DIST � 10)AND(COUNT 6= 3)
Three networks to implement the controller are shown in Figure 11.24. Each network uses a
di�erent approach to control the CNT and LOAD inputs. The �rst and second implementations
makes LOAD = CNT ', which forces the counter to be counting or loading in each clock cycle. In
the �rst implementation, the CNT input is:
CNT = S
0
:GO + S
1
:C + S
2
The second implementation is based on the generation of the LOAD input as:
LOAD = S
0
:GO
0
+ S
1
(A+B) + S
3
+ S
4
+ S
5
The third implementation uses the fact that LOAD overides the CNT input, and the counter
is always counting, by default. The LOAD input has the same circuit as the one used for imple-
mentation 2.
The combinational network for each parallel input (I
j
) is the same for all 3 networks. These
gate networks are obtained from the following table and Kmaps.
Solutions Manual - Introduction to Digital Design - July 1, 1999 233
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
0 0I2 I0GO’
0
1
1
1
1
1
0
1
2
3
4
5
6
72 1 0
MUX
E
1
Q2 Q1 Q0
Q2 Q1 Q0
clear
(b) implementation 2
A+B
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
0 0I2 I0GO’
0
1
1
1
1
1
0
1
2
3
4
5
6
72 1 0
MUX
E
1
Q2 Q1 Q0
Q2 Q1 Q0
clear
(c) implementation 3
1
A+B
A
Q0
Q1
Q2
I2
I0
Q1
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
0 0I2 I0GO
1
0
0
0
0
0
0
1
2
3
4
5
6
72 1 0
MUX
E
1
Q2 Q1 Q0
Q2 Q1 Q0
clear
(a) implementation 1
C
Figure 11.24: Networks to implement the controller in Exercise 11.18
PS Parallel input
Q
2
Q
1
Q
0
I
2
I
1
I
0
000 000
001 10A
010 |
011 001
100 001
101 101
The table has a special parallel input value for state S
1
, when condition A determines the value
of the least signi�cant bit (next state is 5 if condition A is true, 4 otherwise).
I
2
:
0 1 0
-
0 1
- -
Q
0
Q
1
Q
2
I
1
:
0 0 0
-
0 0
- -
Q
0
Q
1
Q
2
I
0
:
0
A
1
-
1 1
- -
Q
0
Q
1
Q
2
I
2
= Q
0
1
Q
0
I
1
= 0
I
0
= Q
1
+Q
2
+Q
0
A
234 Solutions Manual - Introduction to Digital Design - July 1, 1999
The gate networks for I
j
are shown in Figure 11.24 for implementation 1 only, but it is the
same for all other implementations.
Exercise 11.19:
We use up-counting for (s(t)+1) mod 10 function. Since the counter is module-16, it is necessary
to detect when the counter state is 9 and load a 0. Similarly, the count-down feature is used for
(s(t) � 1) mod 8. For this case the value 7 has to be loaded whenever the counter state is 0, and
the value 0 is loaded whenever the count is 9 (since (9 � 1) mod 8 = 0). Consequently, if LOAD
overrides the count signals, we get:
Count� up =
(
1 if (x = 1)
0 otherwise
(11:4)
Count� down =
(
1 if (x = 2)
0 otherwise
(11:5)
LOAD =
(
1 if ((x = 1 or x = 2) and s(t) = 9) or (x = 2 and s(t) = 0)
0 otherwise
(11:6)
The value to be loaded is
i =
8
>
<
>
:
0 if s(t) = 9
7 if s(t) = 0
don't care otherwise
(11:7)
For the binary implementation it is necessary to encode x into binary variables. We choose a binary
enconding such that x = 2x
1
+ x
0
. This results in
Count� up = x
0
Count� down = x
1
LOAD = Q
3
Q
0
(x
1
+ x
0
) + x
1
Q
0
3
Q
0
2
Q
0
1
Q
0
0
I
3
= 0
I
2
= I
1
= I
0
= Q
0
3
The corresponding network is presented in Figure 11.25.
Exercise 11.20:
The state diagram is shown in Figure 11.26. The state names represent even number of 1s (with
an \e" subscript) and odd number of 1s (with an \o" subscript). From the diagram we obtain the
following expressions for the counter control inputs:
CNT = A
e
x
0
+B
e
x+ C
o
x+D
e
x+A
o
x
0
+B
o
x+C
e
x+D
o
x
LOAD = CNT
0
Consider the following state codes:
Solutions Manual - Introduction to Digital Design - July 1, 1999 235
LD
CK
DOWN
CLR
Modulo-16
Counter
Q3 Q2 Q1 Q0
I3 I2 I1 I0
Q3 Q2 Q1 Q0
clear
CK
UP
x1
x0
0
Q3
x1
Q3
Q0
x1
Q3
Q0
x0
Q3’
Q2’
Q1’
Q0’
Figure 11.25: Exercise 11.19
State code
A
e
0
B
e
1
C
e
6
D
e
3
A
o
4
B
o
5
C
o
2
D
o
7
The expressions for the parallel inputs, outputs and CNT are obtained from Kmaps:
I
2
= Q
2
Q
0
+Q
0
2
Q
0
0
= (Q
2
�Q
0
)
0
I
1
= 0
I
0
= Q
1
+Q
0
z
0
= Q
2
z
1
= x+Q
0
1
+Q
0
0
CNT = xQ
0
+ xQ
1
+ x
0
Q
0
1
Q
0
0
The network for this system is shown in Figure 11.27.
Exercise 11.21:
From the network we get:
J = Q
0
0
K = Q
1
Q
0
As only the leftmost FF is of JK type, we can write the following table:
236 Solutions Manual - Introduction to Digital Design - July 1, 1999
Ae Be Ce De
Ao Bo Co Do
0/
1/ 1/
0/
1/
0/
0/
0/
0/
1/
1/
1/
1/
1/
0/0
0/1
when the output is not shown
2 or 3 can be used as output
Figure 11.26: State diagram - Exercise 11.20
Present State Leftmost FF Next State
Q
3
Q
2
Q
1
Q
0
JK Q
3
Q
2
Q
1
Q
0
0000 10 1000
000100 0000
0010 10 1001
0011 01 0001
0100 10 1010
0101 00 0010
0110 10 1011
0111 01 0011
1000 10 1100
1001 00 1100
1010 10 1101
1011 01 0101
1100 10 1110
1101 00 1110
1110 10 1111
1111 01 0111
The state diagram that corresponds to this transition table is presented in Figure 11.28.
Some of the states are transitory states. Others are part of a cycle that represents a counter
behavior. This type of counter is called twisted tail counter. Figure 11.15 of the textbook describes
this counter.
As we can see from the state diagram, it's a self starting counter, since there's always a path
from any state to the main counter cycle. The additional NAND gate (when compared to the
design shown in the textbook) is used for self-starting feature.
Solutions Manual - Introduction to Digital Design - July 1, 1999 237
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
0 0
Q0
Q1
Q0
Q2
Q2 Q1 Q0
x
Q0
x
Q1
x’
Q1’
Q0’
Figure 11.27: Network for Exercise 11.20
0 8 12 14 15
1 3 7
13
10
4
9
2
5116
Figure 11.28: State diagram for the circuit in Exercise 11.21
Exercise 11.22:
Shift input overides LOAD. The loaded value is always (0111)
2
. The SHIFT input is expressed
as:
SHIFT = (Q
3
Q
1
Q
0
)
0
= Q
0
3
+Q
0
1
+Q
0
0
Based on the network we obtain the following table for state transitions:
238 Solutions Manual - Introduction to Digital Design - July 1, 1999
PS SHIFT NS
Q
3
Q
2
Q
1
Q
0
0000 1 1000
0001 1 0000
0010 1 1001
0011 1 0001
0100 1 1010
0101 1 0010
0110 1 1011
0111 1 0011
1000 1 1100
1001 1 0100
1010 1 1101
1011 0 0111
1100 1 1110
1101 1 0110
1110 1 1111
1111 0 0111
The state diagram for the system is presented in Figure 11.29. We can see from the Figure that
the main loop consists of the sequence: 0,8,12,14,15,7,3,1,0.... Any other state, di�erent than those
in the main loop will be in a path that ends in state 7 (that is part of the main loop). Thus, the
counter is self starting. It is a twisted-tail counter.
0 8 12 14
15731
2 45
6 1311
109
Figure 11.29: State diagram for Exercise 11.22
Exercise 11.23: Using two modulo-16 binary counters we implement cascade and parallel
counters for the cases:
(a) a cascade implementation of a modulo-23 counter is shown in Figure 11.30. The state 22,
Q = 10110 is detected and the counter is loaded with the value 0.
The parallel implementation of the same counter uses a modulo-8 and a modulo-3 counter that
together form a modulo-24 parallel counter. The counting sequence, considering T = (T
1
T
0
) as the
output of the modulo-3 counter and E = (E
2
E
1
E
0
) as the output of the modulo-8 counter is given
by the following table:
Solutions Manual - Introduction to Digital Design - July 1, 1999 239
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
0 0 0 0
Q4
TCQ4Q2
Q1
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
x
clear
0 0 0 0
Q3 Q2 Q1 Q0
Figure 11.30: Cascade implementation of modulo-23 counter - Exercise 11.23(a)
state T
1
T
0
E
2
E
1
E
0
0 00 000
1 01 001
2 10 010
3 00 011
4 01 100
5 10 101
6 00 110
7 01 111
8 10 000
9 00 001
10 01 010
11 10 011
12 00 100
13 01 101
14 10 110
15 00 111
16 01 000
17 10 001
18 00 010
19 01 011
20 10 100
21 00 101
22 01 110
23 10 111
The state code is given by the two counters' output, (T;E). For simplicity we represent the
state code using decimal numbers. To modify this modulo-24 counter to a modulo-23 counter, state
22 is detected, which is represented by the code (1; 6), and the state 0, coded as (0; 0) is loaded, as
shown in Figure 11.31.
(b) an 11-to-29 counter. A total of 19 states are needed. The cascade implementation of this
counter is shown in Figure 11.32. Observe that state 29 (11101) is detected and generates a load
signal. The value loaded corresponds to state 11 (1011).
The parallel implementation of this counter uses a modulo-30 parallel counter that is obtained
combining a modulo-5 and a modulo-6 counter. The state sequence, assuming that the state is
composed by (E; T ), where E = (E
2
E
1
E
0
) is the state of the modulo-5 counter and T = (T
2
T
1
T
0
)
is the state code of the modulo-6 counter, is presented (in decimal) in the following table:
240 Solutions Manual - Introduction to Digital Design - July 1, 1999
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
x
clear
E2 E1 E0
T1 T0
TC
0 0 0 0
0 0 0 0
modulo-8
counter
modulo-3
counter
T1
T0
E2
E1
E0
Figure 11.31: Parallel implementation of modulo-23 counter - Exercise 11.23(a)
x
clear
TC
Q4
Q3
Q2
Q0
detects
state 29
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
1 0 1 1
Q3 Q2 Q1 Q0
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
0 0 0 0
Q4
Figure 11.32: Cascade implementation of a 11-to-29 counter - Exercise 11.23(b)
state E T state E T
0 0 0 15 0 3
1 1 1 16 1 4
2 2 2 17 2 5
3 3 3 18 3 0
4 4 4 19 4 1
5 0 5 20 0 2
6 1 0 21 1 3
7 2 1 22 2 4
8 3 2 23 3 5
9 4 3 24 4 0
10 0 4 25 0 1
11 1 5 26 1 2
12 2 0 27 2 3
13 3 1 28 3 4
14 4 2 29 4 5
Thus, to obtain the 11-to-29 counter we need to detect state 29 (4; 5) and load state 11 (1; 5).
Solutions Manual - Introduction to Digital Design - July 1, 1999 241
The network is shown in Figure 11.33.
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
E2 E1 E0
T2 T1 T0
0 0 
0 0 0 
x
clear
modulo-5
counter
TC
modulo-6
counter
E2
Figure 11.33: Parallel implementation of a 11-to-29 counter - Exercise 11.23(b)
(c) a frequency divider by 27
For the cascade implementation, the state (11010) is detected and the value 0 is loaded as the
next state. The same load signal (TC) is the output of the frequency divider. The network is shown
in Figure 11.34.
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
x
clear
0 0 0 0 0 0 0 0
Q3 Q2 Q1 Q0Q4
Q4
Q3
Q1
detects
state 26
zTC
Figure 11.34: Cascade implementation of a frequency divider by 27 - Exercise 11.23(c)
The parallel implementation makes use of a modulo-4 and a modulo-7 counter to obtain a
modulo-28 counter. The state code is represented by two components (E; T ), where E = (E
1
E
0
)
is the state code for the modulo-4 counter and T = (T
2
T
1
T
0
) is the state code of the modulo-7
counter. When state 26 (2; 5) is reached, both counters are loaded with the initial state 0. The
network shown in Figure 11.35 shows the parallel implementation of this frequency divider. The
242 Solutions Manual - Introduction to Digital Design - July 1, 1999
circuit output corresponds to the load signal (TC).
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
 T1 T0
E1 E0
0 0 0 0
0 0 0 0
x
clear
modulo-7
counter
 T2
z
TC
E1
E0’ T2T1’ T0
Figure 11.35: Parallel implementation of a frequency divider by 27 - Exercise 11.23(c)
Exercise 11.24: We notice that the counting sequencecan be described by the following nested
loops:
for i=0 to 14 do
for j=i to 15 do
z=j
endfor
endfor
Consequently, to implement this counter we can use one mod-16 counter for each loop. The
output of the counter in the inner loop (counter 2) is z = j, and the output of the counter in
the outer loop (counter 1) is i. The implementation is shown in Figure 11.36. The counter on
top (counter 1) is a modulo-15 counter (counts from 0 to 14) and provides a loading value for
the bottom counter (counter 2). Every time counter 2 loads the value on its parallel inputs (I
i
),
counter 1 goes to its next state. Counter 1 counts the number of TCs from counter 2 (when counter
2 reaches 15). However, counter 1 must be initialized with value 1 when the clear signal is issued.
That happens because counter 2 will start counting from zero after the clear signal (no load is
needed), and after 15 cycles its TC output becomes a 1, and the value to be loaded must be 1. For
this reason the clear signal is connected to input I
0
of counter 1 and it is combined with the \state
14" signal to generate the correct load input.
Solutions Manual - Introduction to Digital Design - July 1, 1999 243
LD
CK
CNT
CLR
Modulo-16
CounterCK
I3 I2 I1 I0
Q3 Q2 Q1 Q0
LD
CK
CNT
CLR
Modulo-16
Counter
Q3 Q2 Q1 Q0
CK
I3 I2 I1 I0
Q3 Q2 Q1 Q0
TC
TC
1
clear
state
14
0 0 0 0
Figure 11.36: Network for Exercise 11.24
Exercise 11.25:
The counter shown in Figure 11.37 of the text is a mod-24 parallel counter composed of a
modulo-3 counter and a modulo-8 counter (twisted-tail counter). It has the following sequence of
state values:
modulo-3 modulo-8
Q
1
Q
0
q
0
q
1
q
2
q
3
00 0000
01 1000
10 1100
00 1110
01 1111
10 0111
00 0011
01 0001
10 0000
00 1000
01 1100
10 1110
00 1111
01 0111
10 0011
00 0001
01 0000
10 1000
00 1100
01 1110
10 1111
00 0111
01 0011
10 0001
244 Solutions Manual - Introduction to Digital Design - July 1, 1999
Observe that the output z is 1 when Q
1
Q
0
q
0
q
1
q
2
q
3
= 100001, that corresponds to the expression
z = Q
1
Q
0
0
q
0
2
q
3
, and is equivalent to a Terminal Count (TC) signal in a binary counter.
(a) a binary modulo-24 autonomous counter using T 
ip 
ops and gates is shown in Figure 11.37.
State 23 (10111) is detected by a network that implements the expression S
23
= Q
4
Q
2
Q
1
Q
0
. Since
the next state from (10111) must be (00000), we need T
0
= T
1
= T
2
= T
4
= 1 and T
3
= 0. The
values of T
0
= T
1
= T
2
= 0 are already generated when the present state is (10111). The values
T
4
= 1 and T
3
= 0 must be forced when S
23
= 1. The implementation has fewer 
ip 
ops, more
gates and more connections than the implementation in Figure 11.37 of the text.
T Q T Q T Q T Q T Q
CK
1 Q4
Q3Q2Q1Q00 1 2 3 4
Q4
Q2
Q1
Q0
S23
z
Figure 11.37: Modulo-24 autonomous counter - Exercise 11.25(a)
(b) a twisted-tail modulo-24 autonomous counter using D 
ip 
ops and gates is shown in
Figure 11.38. Twelve 
ip 
ops are needed, instead of the six 
ip-
ops used in Figure 11.37 of the
text. However, no gates are required and besides the clock line, all interconnections can be made
very short. The TC condition is generated when the present state is (000000000001), and that is
the only state when we have a 0 preceding a 1 at the rightmost 
ip 
op.
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
1 2 3 4 12
CK
z
Figure 11.38: Twisted-tail modulo-24 autonomous counter - Exercise 11.25(b)
Exercise 11.26:
(a) The network is shown in Figure 11.39. The right counter is a modulo-5 counter. Taking only
into account the state bits (Q
2
Q
1
Q
0
), the left counter in the Figure corresponds to a \subcounter"
that is modulo 8. When the state of the modulo-5 counter is 100 and the state of the other counter
is 111, the output z becomes 1. For all other states, z = 0. As we have 40 di�erent states, and
z = 1 only once, the circuit implements a modulo-40 frequency divider.
Solutions Manual - Introduction to Digital Design - July 1, 1999 245
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
CK
11
clearclear
0
0 0 0 00 0 0 0
z
Figure 11.39: Modulo-40 frequency divider - Exercise 11.26(a)
(b) the counting sequence of a counter formed by a modulo-10 and a modulo-4 counter is:
(0,0), (1,1), (2,2), (3,3), (4,0), (5,1), (6,2), (7,3), (8,0), (9,1), (0,2), (1,3), (2,0), (3,1), (4,2),
(5,3), (6,0), (7,1), (8,2), (9,3), (0,0), : : :
Observe that although 4x10=40 this is a modulo-20 counter instead of a modulo-40 counter
because 4 and 10 are not relatively prime.
Exercise 11.27: The state diagram for the electronic lock is shown in Figure 11.40. Such a
state diagram is adequately implemented using a modulo-16 counter and a 16-input multiplexer.
In order to generate the required outputs, another counter is used to count the number of times the
buttons were pressed. This counter generates a signal END when the keys were pressed 12 times.
We assume that the outputs of the push buttons that generate the inputs are 1s for only one clock
Init A1 A2 A3 A4 A5 C1 C2 C3 B1 B2 B3
Error
B4A A
B,C
A A A C C C B B B B
B,C B,C B,C B,C A,B A,B A,B A,C A,C A,C A,C
A,B,C
Figure 11.40: State Diagram for the electronic lock - Exercise 11.27
period, each time the user press them. A network for this task is shown in Figure 11.41 together
with the network that implements the lock controller. When a correct sequence is inserted (state
is B4) the output z = 1 is generated, and the controller goes back to the initial state. When a
wrong sequence is inserted the RED output is activated by the condition B4
0
� END (END = 1
when 12 characters were inserted). The output GREEN is 1 when the controller is at state INIT .
The Y ELLOW is 1 while the sequence is being inserted, that means, the sequence started to be
inserted and the RED or z output were not generated yet. When z = 0 the top counter goes to
state 15 (ERROR), and the bottom one stays at state 12. Only a reset signal R will remove the
counters from these states, if the wrong sequence is inserted. When z = 1 both counters load the
246 Solutions Manual - Introduction to Digital Design - July 1, 1999
value 0 and they are ready to start another operation.
R
0 0 0 0
A
B
C z
RED
GREEN
YELLOW
D Q
Q
push button
CK
circuit used to obtain A, B, and C
CK
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
e
CK
CNT
CLR
LD q3 q2 q1 q0
I3 I2 I1 I0
TCMod-16 Counter
B4
R
3 2 1 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MUX
z
A
A
A
A
A
C
C
C
B
B
B
B
0
0
0
0
Figure 11.41: Sequential Lock network - Exercise 11.27
Solutions Manual - Introduction to Digital Design - July 1, 1999 247
Exercise 11.28: The design of this controller can be done using an approach similar to the
one presented in Figure 11.21 of the text. The network is shown in Figure 11.42.
CNT
CLR
LD q2 q1 q0
 I2 I1 I0
TCMod-6 Counter
CK
NEQ
clear
CNT
CLR
LD q4 q3 q2 q1 q0
I4 I3 I2 I1 I0
TCMod-32 Counter
CK
clear
Decoder
0 1 2 3 4 5
0 0
n
5
5-bit Comparator
NEQ
S
R
Q
CK
S
R
Q
CK
S
R
Q
CK
S
R
Q
CK
c0
c1
c2
c3
2 10 a4 a3 a2 a1 a0 b
a<b
Figure 11.42: Controller - Exercise 11.28
Exercise 11.29: The network to perform the comparison x(t� 7; t� 4) < x(t� 3; t) is shown
in Figure 11.43.
Left-shift Register serialinputCK
4-bit comparator
A3 A2 A1 A0 B3 B2 B1 B0
x
A>B A=B A<B
z
Figure 11.43: Network for Exercise 11.29