Gustavo_Molina_LAB2

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Video Prática 2.mp4
Tabelas Verdade.pdf
Tabelas verdade 
 
1.A 
 
A B \(X+Y) \X\Y 
0 0 1 1 
0 1 0 0 
1 0 0 0 
1 1 0 0 
 
1.B 
A B \(XY) \X+\Y 
0 0 1 1 
0 1 1 1 
1 0 1 1 
1 1 0 0 
 
2.A 
A1 B1 C1 D1 Saída 
0 0 0 0 0 
0 0 0 1 0 
0 0 1 0 0 
0 0 1 1 1 
0 1 0 0 0 
0 1 0 1 0 
0 1 1 0 0 
0 1 1 1 0 
1 0 0 0 0 
1 0 0 1 0 
1 0 1 0 0 
1 0 1 1 0 
1 1 0 0 0 
1 1 0 1 0 
1 1 1 0 0 
1 1 1 1 0 
 
 
 
 
 
 
2.B 
A2 B2 C2 Saída 
0 0 0 0 
0 0 1 0 
0 1 0 0 
0 1 1 0 
1 0 0 0 
1 0 1 0 
1 1 0 0 
1 1 1 1 
 
2.C 
A3 B3 C3 D3 Saída 
0 0 0 0 1 
0 0 0 1 1 
0 0 1 0 0 
0 0 1 1 1 
0 1 0 0 0 
0 1 0 1 0 
0 1 1 0 0 
0 1 1 1 0 
1 0 0 0 1 
1 0 0 1 1 
1 0 1 0 0 
1 0 1 1 0 
1 1 0 0 0 
1 1 0 1 0 
1 1 1 0 0 
1 1 1 1 0 
 
 
EX1_LS/EX1A_LS.circ
 
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
EX1_LS/EX1B_LS.circ
 
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
EX2_LS/EX2A_LS.circ
 
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
EX2_LS/EX2B_LS.circ
 
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
EX2_LS/EX2C_LS.circ
 
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
EX1_Q/A/db/.cmp.kpt
EX1_Q/A/db/EX1Aa_Q.(0).cnf.cdb
EX1_Q/A/db/EX1Aa_Q.(0).cnf.hdb
EX1_Q/A/db/EX1Aa_Q.asm.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615336719845 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615336719845 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 09 21:38:39 2021 " "Processing started: Tue Mar 09 21:38:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615336719845 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1615336719845 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off EX1Aa_Q -c EX1Aa_Q " "Command: quartus_asm --read_settings_files=off --write_settings_files=off EX1Aa_Q -c EX1Aa_Q" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1615336719846 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1615336720096 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1615336720109 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1615336720113 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4668 " "Peak virtual memory: 4668 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615336720249 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 09 21:38:40 2021 " "Processing ended: Tue Mar 09 21:38:40 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615336720249 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615336720249 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615336720249 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1615336720249 ""}
EX1_Q/A/db/EX1Aa_Q.asm.rdb
EX1_Q/A/db/EX1Aa_Q.asm_labs.ddb
EX1_Q/A/db/EX1Aa_Q.cbx.xml
 
	 
	
EX1_Q/A/db/EX1Aa_Q.cmp.cdb
EX1_Q/A/db/EX1Aa_Q.cmp.hdb
EX1_Q/A/db/EX1Aa_Q.cmp.idb
EX1_Q/A/db/EX1Aa_Q.cmp.logdb
v1
EX1_Q/A/db/EX1Aa_Q.cmp.rdb
EX1_Q/A/db/EX1Aa_Q.cmp0.ddb
EX1_Q/A/db/EX1Aa_Q.db_info
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Wed Mar 10 16:11:01 2021
EX1_Q/A/db/EX1Aa_Q.fit.qmsg
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading
on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1615336718302 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1615336718302 ""}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "EX1Aa_Q EPM240T100C3 " "Automatically selected device EPM240T100C3 for design EX1Aa_Q" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1615336718359 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1615336718424 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615336718428 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C3 " "Device EPM570T100C3 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615336718487 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615336718487 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EX1Aa_Q.sdc " "Synopsys Design Constraints File file not found: 'EX1Aa_Q.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1615336718508 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1615336718509 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1615336718509 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615336718509 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1615336718510 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1615336718510 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Fitter" 0 -1 1615336718510 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615336718510 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615336718511 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615336718511 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1615336718512 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1615336718512 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1615336718512 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1615336718518 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1615336718523 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1615336718523 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1615336718523 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615336718523 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OSC_CLK " "Node \"OSC_CLK\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OSC_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SP1 " "Node \"SP1\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SP1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SP2 " "Node \"SP2\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SP2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[0\] " "Node \"c_7s\[0\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment
Editor.qase" 1 { { 0 "c_7s\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[1\] " "Node \"c_7s\[1\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[2\] " "Node \"c_7s\[2\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[3\] " "Node \"c_7s\[3\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[4\] " "Node \"c_7s\[4\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[5\] " "Node \"c_7s\[5\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[6\] " "Node \"c_7s\[6\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "chave\[0\] " "Node \"chave\[0\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "chave\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "chave\[1\] " "Node \"chave\[1\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "chave\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "chave\[2\] " "Node \"chave\[2\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "chave\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "chave\[3\] " "Node \"chave\[3\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "chave\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "chave_C " "Node \"chave_C\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "chave_C" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "chave_D " "Node \"chave_D\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "chave_D" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "d_7s\[0\] " "Node \"d_7s\[0\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "d_7s\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "d_7s\[1\] " "Node \"d_7s\[1\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "d_7s\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "d_7s\[2\] " "Node \"d_7s\[2\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "d_7s\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "d_7s\[3\] " "Node \"d_7s\[3\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "d_7s\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "d_7s\[4\] " "Node \"d_7s\[4\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "d_7s\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "d_7s\[5\] " "Node \"d_7s\[5\]\" is assigned to location or region, but does not exist in design"
{ } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "d_7s\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "d_7s\[6\] " "Node \"d_7s\[6\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "d_7s\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "led\[1\] " "Node \"led\[1\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "led\[2\] " "Node \"led\[2\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "led\[3\] " "Node \"led\[3\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "led\[4\] " "Node \"led\[4\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "led\[5\] " "Node \"led\[5\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "led\[6\] " "Node \"led\[6\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "led\[7\] " "Node \"led\[7\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_1 " "Node \"p4_1\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_10 " "Node \"p4_10\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_10" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_11 " "Node \"p4_11\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_11" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_12 " "Node \"p4_12\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_12" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_13 " "Node \"p4_13\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_13" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_14 " "Node \"p4_14\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_14" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_15 " "Node \"p4_15\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_15" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_16 " "Node \"p4_16\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_16" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_17 " "Node \"p4_17\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_17" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_18 " "Node \"p4_18\" is assigned to location or region, but does not exist in design"
{ } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_18" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_19 " "Node \"p4_19\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_19" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_2 " "Node \"p4_2\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_20 " "Node \"p4_20\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_20" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_3 " "Node \"p4_3\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_3" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_4 " "Node \"p4_4\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_4" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_5 " "Node \"p4_5\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_5" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_6 " "Node \"p4_6\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_6" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_7 " "Node \"p4_7\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_7" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_8 " "Node \"p4_8\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_8" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "p4_9 " "Node \"p4_9\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "p4_9" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_1 " "Node \"pio_1\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_2 " "Node \"pio_2\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_3 " "Node \"pio_3\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_3" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_4 " "Node \"pio_4\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_4" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_5 " "Node \"pio_5\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_5" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_6 " "Node \"pio_6\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_6" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_7 " "Node \"pio_7\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_7" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_8 " "Node \"pio_8\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment
Editor.qase" 1 { { 0 "pio_8" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_9 " "Node \"pio_9\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_9" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_A " "Node \"pio_A\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_A" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_B " "Node \"pio_B\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_B" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_C " "Node \"pio_C\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_C" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_D " "Node \"pio_D\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_D" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_E " "Node \"pio_E\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_E" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_F " "Node \"pio_F\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_F" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_G " "Node \"pio_G\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_G" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_H " "Node \"pio_H\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_H" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "pio_I " "Node \"pio_I\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "pio_I" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615336718526 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1615336718526 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615336718529 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1615336718532 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1615336718601 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615336718615 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1615336718617 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1615336718653 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615336718654 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1615336718662 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/WINDOWS 10/Desktop/Projetos Quartus/EX1_Q/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1615336718705 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1615336718705 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1615336718720 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING"
"" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1615336718720 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1615336718720 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615336718721 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.04 " "Total time spent on timing analysis during the Fitter is 0.04 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1615336718727 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615336718734 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1615336718740 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/WINDOWS 10/Desktop/Projetos Quartus/EX1_Q/output_files/EX1Aa_Q.fit.smsg " "Generated suppressed messages file C:/Users/WINDOWS 10/Desktop/Projetos Quartus/EX1_Q/output_files/EX1Aa_Q.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1615336718778 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 75 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 75 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5521 " "Peak virtual memory: 5521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615336718855 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 09 21:38:38 2021 " "Processing ended: Tue Mar 09 21:38:38 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615336718855 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615336718855 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615336718855 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1615336718855 ""}
EX1_Q/A/db/EX1Aa_Q.hier_info
|EX1Aa_Q
led[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
chave_B => inst.IN0
chave_A => inst.IN1
EX1_Q/A/db/EX1Aa_Q.hif
EX1_Q/A/db/EX1Aa_Q.lpc.html
		Hierarchy		Input		Constant Input		Unused Input		Floating Input		Output		Constant Output		Unused Output		Floating Output		Bidir		Constant Bidir		Unused Bidir		Input only Bidir		Output only Bidir
EX1_Q/A/db/EX1Aa_Q.lpc.rdb
EX1_Q/A/db/EX1Aa_Q.lpc.txt
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
EX1_Q/A/db/EX1Aa_Q.map.cdb
EX1_Q/A/db/EX1Aa_Q.map.hdb
EX1_Q/A/db/EX1Aa_Q.map.logdb
v1
EX1_Q/A/db/EX1Aa_Q.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615336709148 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615336709148 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 09 21:38:29 2021 " "Processing started: Tue Mar 09 21:38:29 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615336709148 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615336709148 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EX1Aa_Q -c EX1Aa_Q " "Command: quartus_map --read_settings_files=on --write_settings_files=off EX1Aa_Q -c EX1Aa_Q" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615336709148 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1615336709438 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1615336709438 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex1aa_q.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ex1aa_q.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EX1Aa_Q " "Found entity 1: EX1Aa_Q" { } { { "EX1Aa_Q.bdf" "" { Schematic "C:/Users/WINDOWS 10/Desktop/Projetos Quartus/EX1_Q/EX1Aa_Q.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615336716677 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615336716677 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output_files/ex1ab_q.bdf 1 1 " "Found 1 design units, including 1 entities, in source file output_files/ex1ab_q.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EX1Ab_Q " "Found entity 1: EX1Ab_Q" { } { { "output_files/EX1Ab_Q.bdf" "" { Schematic "C:/Users/WINDOWS 10/Desktop/Projetos Quartus/EX1_Q/output_files/EX1Ab_Q.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1615336716679 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1615336716679 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "EX1Aa_Q " "Elaborating entity \"EX1Aa_Q\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1615336716706 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1615336716875 ""} { "Info" "ICUT_CUT_TM_OPINS"
"1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1615336716875 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1615336716875 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1615336716875 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4709 " "Peak virtual memory: 4709 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615336716952 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 09 21:38:36 2021 " "Processing ended: Tue Mar 09 21:38:36 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615336716952 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615336716952 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615336716952 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1615336716952 ""}
EX1_Q/A/db/EX1Aa_Q.map.rdb
EX1_Q/A/db/EX1Aa_Q.pre_map.hdb
EX1_Q/A/db/EX1Aa_Q.root_partition.map.reg_db.cdb
EX1_Q/A/db/EX1Aa_Q.routing.rdb
EX1_Q/A/db/EX1Aa_Q.rtlv.hdb
EX1_Q/A/db/EX1Aa_Q.rtlv_sg.cdb
EX1_Q/A/db/EX1Aa_Q.rtlv_sg_swap.cdb
EX1_Q/A/db/EX1Aa_Q.sld_design_entry.sci
EX1_Q/A/db/EX1Aa_Q.sld_design_entry_dsc.sci
EX1_Q/A/db/EX1Aa_Q.smart_action.txt
DONE
EX1_Q/A/db/EX1Aa_Q.sta.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615336721454 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615336721455 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 09 21:38:41 2021 " "Processing started: Tue Mar 09 21:38:41 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615336721455 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1615336721455 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta EX1Aa_Q -c EX1Aa_Q " "Command: quartus_sta EX1Aa_Q -c EX1Aa_Q" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1615336721455 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1615336721557 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1615336721650 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1615336721650 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1615336721721 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1615336721738 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EX1Aa_Q.sdc " "Synopsys Design Constraints File file not found: 'EX1Aa_Q.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1615336721784 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1615336721784 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1615336721784 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1615336721785 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1615336721785 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1615336721790 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615336721795 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1615336721798 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615336721803 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615336721808 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615336721812 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615336721819 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1615336721822 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1615336721823 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1615336721835 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1615336721835 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing
Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615336721894 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 09 21:38:41 2021 " "Processing ended: Tue Mar 09 21:38:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615336721894 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615336721894 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615336721894 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1615336721894 ""}
EX1_Q/A/db/EX1Aa_Q.sta.rdb
EX1_Q/A/db/EX1Aa_Q.sta_cmp.3_slow.tdb
EX1_Q/A/db/EX1Aa_Q.tis_db_list.ddb
EX1_Q/A/db/EX1Aa_Q.vpr.ammdb
EX1_Q/A/db/EX1Ab_Q.(0).cnf.cdb
EX1_Q/A/db/EX1Ab_Q.(0).cnf.hdb
EX1_Q/A/db/EX1Ab_Q.asm.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1615337304879 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1615337304879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 09 21:48:24 2021 " "Processing started: Tue Mar 09 21:48:24 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1615337304879 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1615337304879 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off EX1Ab_Q -c EX1Ab_Q " "Command: quartus_asm --read_settings_files=off --write_settings_files=off EX1Ab_Q -c EX1Ab_Q" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1615337304879 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1615337305141 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1615337305155 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1615337305162 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4668 " "Peak virtual memory: 4668 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1615337305306 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 09 21:48:25 2021 " "Processing ended: Tue Mar 09 21:48:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1615337305306 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1615337305306 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1615337305306 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1615337305306 ""}
EX1_Q/A/db/EX1Ab_Q.asm.rdb
EX1_Q/A/db/EX1Ab_Q.asm_labs.ddb
EX1_Q/A/db/EX1Ab_Q.cbx.xml
 
	 
	
EX1_Q/A/db/EX1Ab_Q.cmp.cdb
EX1_Q/A/db/EX1Ab_Q.cmp.hdb
EX1_Q/A/db/EX1Ab_Q.cmp.idb
EX1_Q/A/db/EX1Ab_Q.cmp.logdb
v1
EX1_Q/A/db/EX1Ab_Q.cmp.rdb
EX1_Q/A/db/EX1Ab_Q.cmp0.ddb
EX1_Q/A/db/EX1Ab_Q.db_info
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Tue Mar 09 21:43:48 2021
EX1_Q/A/db/EX1Ab_Q.fit.qmsg
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1615337303362 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1615337303363 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "EX1Ab_Q EPM240T100C5 " "Selected device EPM240T100C5 for design \"EX1Ab_Q\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1615337303365 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615337303399 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615337303399 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1615337303450 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615337303453 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615337303513 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615337303513 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615337303513 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615337303513 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1615337303513 ""} } { } 2 176444 "Device migration not selected. If you intend
to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615337303513 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EX1Ab_Q.sdc " "Synopsys Design Constraints File file not found: 'EX1Ab_Q.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1615337303533 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1615337303533 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1615337303534 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615337303534 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1615337303535 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1615337303535 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Fitter" 0 -1 1615337303535 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1615337303535 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615337303535 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615337303535 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1615337303537 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1615337303537 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1615337303537 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1615337303543 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1615337303549 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1615337303549 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1615337303549 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615337303549 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OSC_CLK " "Node \"OSC_CLK\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OSC_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615337303553 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SP1 " "Node \"SP1\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SP1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615337303553 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SP2 " "Node \"SP2\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SP2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615337303553 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[0\] " "Node \"c_7s\[0\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615337303553 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[1\] " "Node \"c_7s\[1\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615337303553 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[2\] " "Node \"c_7s\[2\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615337303553 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[3\] " "Node \"c_7s\[3\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1615337303553 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "c_7s\[4\] " "Node \"c_7s\[4\]\" is assigned to location or region, but does not exist in design" { } { { "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "c_7s\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned