Impact_of_RF-based_fault_injection_in_Pierce-type_crystal_oscillators_under_EMC_standard_tests_in_microcontrollers

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Impact of RF-Based Fault Injection in Pierce-type Crystal 
Oscillators under EMC Standard Tests in Microcontrollers 
 
A. Olmos1, A. Vilas Boas2 
Microcontrollers Division 
Freescale Semiconductor 
Austin, USA1 / Campinas, Brazil2 
Contact author: Alfredo.Olmos@freescale.com 
E. R. da Silva3, J. C. Silva3, and R. Maltione3 
Hardware Systems Conception Division 
Center for Technology Information 
Campinas, Brazil3 
Contact author: Ricardo.Maltione@cti.gov.br
 
Abstract — Crystal oscillators are usually implemented using 
Pierce´s configuration due to its high stability, small amount of 
components, and easy adjustment. With technology development 
and device shrinking, modern microcontroller embedded 
oscillators include all network components integrated on chip to 
attend cost-effective designs supporting both crystals and ceramic 
resonators. This fact makes the oscillator more sensitive to 
feedback network load and strays related to the ESD protections 
required at the external crystal I/O pins. Robust applications 
such as industrial, automotive, biomedical, and aerospace require 
aggressive EMC qualification tests where high power RF 
interference is injected causing jitter, frequency deviation, or 
even clock corruption that traduces in severe faults at system 
level. This work discusses the impact of RF interference on 
crystal oscillators. A theoretical load factor analysis is proposed 
and compared to experimental results obtained from a 0.35μm 
CMOS silicon test vehicle. Finally, a test strategy for 
microcontrollers and complex SoCs is presented. 
Keywords – Crystal Oscillators, RF Fault Injection, EMC. 
I. INTRODUCTION 
During several decades Pierce´s oscillator [1,2] have been 
widely used to built clock circuits for microcontrollers (MCUs) 
and several Systems on Chip (SoC). In usual configuration, the 
crystal is often mounted close to the MCU clock pins with a 
small network composed by two capacitors (C1 and C2) tied to 
ground, and a resistor connected in parallel with the crystal; the 
resistor is intended to control crystal drive current and avoid 
overstress and signal distortion in high order harmonics. This 
configuration guarantees great stability if well designed using 
either crystals or ceramic resonators. It is also easy to adjust by 
changing the feedback network components according to the 
manufacturer parameters. 
With the technology shrink and extensive use of MCUs in 
cost-effective applications, the market for on-chip network 
components glowed, even at noisy environments such as 
industrial and automotive [3-7]. In this way, to keep a cost-
effective design, the load capacitors are smaller and sometimes 
comparables to the I/O pad capacitances or to the capacitance 
associated with the ESD structures used to protect the pins. 
In addition, power management constrains for low power 
applications requires that the crystal feedback amplifier 
operates at very low current levels, making the crystal to also 
drive a small current. These oscillators can be set to generate a 
highly accurate clock signal with a few tens of ppm/oC 
stability, required for precision functions such as: input capture 
timers for period measurement; period generation for delay, 
timing, and schedulers; timeout comparison for PWM, 
watchdog, etc.; and to define A/D and D/A conversion rates. 
The excellent performance of Pierce crystal oscillators is 
seriously affected if used in applications under powerful Radio 
Frequency (RF) interference. Hence, this cost-effective solution 
can be disturbed with a high probability occurrence of harsh 
errors or just stopping to work in extreme cases. The literature 
reports several effects of RF interference predicting induced 
failures in complex circuits. For instance, in [8] is presented an 
interesting work about multi-oscillation mode causing 
oscillation locks. The references [6-11] perform analysis 
regarding general noise sources considering aspects as phase 
and 1/f noise [6,9], jitter [10] and substrate noise [11]. Reported 
works related to RF interference are focused on disturbing 
effects [12] in digital circuits caused by change in inverter trip-
point and induced delays in logic gates [9,10]. References [12-
14] analyze aspects of RF interference being applied on analog 
circuits such as comparators (or op-amps) and voltage/current 
references through the changes in its bias points [6,7]. Some 
other aspects related to susceptibility to the interference in ICs 
are presented in [9] depending on the severity of the test 
method (i.e., IEC 62132). Regarding exclusively oscillators, the 
method proposed in [19] for RF interference is more 
appropriate for non-harmonic oscillators. References [21, 22] 
explore the effects of low level of RF interference. Therefore, 
there is a lack of studies on harmonic oscillations under strong 
RF interference. 
The present work examines the impact of interference and 
loading on the Pierce´s oscillators feedback network and its 
influence on the frequency precision, including jitter and 
modulation as well as failure mechanisms that might cause 
upsets under extreme high RF power applied at substrate 
resonance range (that is given by tuning the substrate 
inductance LSUB with the parasitic junction capacitances). 
This work is organized as follows: Section I and II briefly 
study the effect of RF interference on Pierce´s crystal 
oscillators, to identify sources and paths of interference, the 
impact on frequency and stability, and several fault conditions 
in applications. Section III describes a theoretical analysis 
This work was partially sponsored by FAPESP and CNPQ/Brazil 
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introducing a new load factor parameter that helps to 
understand how the feedback network contributes in the 
interference process. Section IV checks the hypothesis by 
simulation regarding the identified failure mechanisms. Finally, 
Section V shows experimental results as well as presents a 
methodology for testing. 
II. RF INTERFERENCE IN PIERCE CRYSTAL OSCILLATORS 
The basic Pierce oscillator circuit is based on a single 
transistor driven by a current source to implement an inverter 
amplifier. This can be performed also using an unbuffered 
inverter as shown in Fig. 1A. An implementation with on-chip 
network components is shown in Fig. 1B. In practical MCU 
implementations external components are used according to 
manufacturer parameters of the crystal or the ceramic 
resonator. The crystal model shown in Fig. 2 depicts the main 
elements (LS1, CS1 - responsible by fundamental oscillation 
frequency), the spurious components (LSK, CSK) and the other 
harmonic overtones (LSN, CSN – restricted to 5th in practice) [8]. 
The present work will study the deviation on the 
fundamental frequency caused by the load, assuming the Q 
factor of the oscillator circuit is enough to maintain it locked 
close to fundamental, although it is still susceptible to RF 
interference. 
Fig. 1B also illustrates the ESD structures related with the 
XTAL1 and XTAL2 I/O pads that provide the interface 
between the on-chip and the external components. 
 
Basically, there are two schemes of ESD protections as 
described in [4]. Fig. 3 shows the transversal section of these 
structures highlighting the main strays associated with them. 
Regarding the oscillation frequency range for crystals operating 
at fundamental mode, and since LS1 is higher than the parasitic 
inductances, it is reasonable to conclude that the main 
interference path occurs via parasitic capacitances that could be 
comparables to the load capacitances present in the feedback 
network. Note that most MCUs have a reduced analog portion 
in contrast with the digital part. Therefore, the rail based 
scheme is preferred over thepad based protections. Hence, the 
main path to interference is through the diodes (to Pbulk and to 
the substrate) via reverse capacitances. This interference occurs 
before reaching the threshold needed to have a rectification 
effect of the interference signal by the protection diodes 
operating in both forward and reverse bias mode. 
In this way, the analysis begins by modeling the 
interference through ZC path (that corresponds to the substrate, 
die flag, bulk well and ESD parasitic) applied to the feedback 
amplifier input as shown in Fig. 4. Based in this model, there 
are two failure mechanisms according to the interference level: 
A) Low to medium interference level 
Failure mechanism: Loading and trip point deviation 
Condition: |VRF-sub | < VDD/k-VD (k � 2), 
In this case the RF interference coupled via ZC impedance 
will affect the average value of the inverter amplifier trip-point 
Figure 1. (A) Pierce´s crystal oscillator, and (B) its main parasitics. 
Figure 2. Equivalent crystal model including fundamental, harmonics and 
spurious oscillation modes. 
Figure 3. ESD protection parasitics considered in node interference analysis: 
(A) Rail based protection; and (B) PAD based protection. 
 
Figure 4. Interference coupling path to the feedback amplifier input. 
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(considering a logic inverter) or changing the bias point that 
will reflect on loop stability conditions. Frequency deviation 
due to trip-point shift and jitter will be induced. 
B) High interference level 
Failure mechanism: Rectification and clock corruption 
Condition: |VRF-sub | � VDD/k-VD (k � 2) 
In this case the RF interference has now enough amplitude 
to put the ESD protections in the forward bias region. Thus, 
rectification phenomena will occur and the load capacitances 
will increase the average value at the input of the inverter 
amplifier (trip-point change, considering a logic inverter) 
carrying it out of the linear operation region until it reaches one 
of the thresholds to switch its output to a permanent state. 
The first failure mechanism is very important because it can 
cause unexpected errors in the system. It is not easily 
identified, and cannot be predicted or fixed. The second failure 
mechanism is clearly easy to identify since a severe issue in the 
system occurs; for instance, during Directly Power Injection 
(DPI) test when the equipment is looking for the maximum 
susceptibility point. Next section proposes an innovative 
analysis based on a new load factor definition to correlate the 
frequency deviation with the loading induced by RF 
interference. 
III. INTERFERENCE ANALYSIS THROUGH LOAD FACTOR 
An interference analysis of the RF injection to the nodes of 
the circuit on Fig. 4 considers the noise coupled just onto the 
sensitive nodes. The RF interference is represented by (VRF, 
ZRF) coupled to node N via ZC (i.e., substrate coupling) or via 
ZF (i.e., flag or “die pad”) where VRF and VX are complex 
signals. Assuming these sources can be expressed by their 
complex Fourier series as: 
T
feAtVeAtV
n
tnj
XX
n
tnj
RFRF
����� 22,)(,)( ���� ��
�
���
�
���
 (1) 
the current across the node N is given by IN=IX+IRF where IX 
represents the normal operation component and IRF the 
interference component. Applying the interference analysis 
described in [11], the VN voltage can be expressed using an 
average constant 1/T with T>TRF regarding the offset due to RF 
interference as: 
)(~)(~)(~ ��� RFCXXN VSVSV �� (2) 
where SX and SC are constants for a certain frequency � and VX 
and VRF are averaged voltages. Notice the amplifier was 
modeled as H(�). This signal returns to node N via the 
feedback network represented by F(�) that includes the crystal 
resonator. 
Under condition (A), the block H(�) could be considered as 
operating in the linear region allowing oscillation if the loop 
gain is enough to guarantee the overall phase shift that satisfies 
the oscillation condition [3,5]. In this case the interference 
affects the closed loop gain and the poles position. So, it might 
cause instability and impact the start-up time. Under condition 
(B), the block H(�) has a non linear behavior (due to 
rectification) causing expressive change in the closed loop gain 
with harmonics generation that will be processed by the 
amplifier. Note that when VN reaches one of the inverter 
thresholds the system collapses and the oscillation stops. 
As discussed before, when the interference is under case 
(A), it is not easy to predict the oscillation deviation in an easy 
way. A possible method is to analyze the effects on the 
feedback network from the loading point of view. Since the 
Pierce oscillator works with a positive reactance [5], the 
relationship between the parallel and series resonance elements 
should be explored. 
The oscillation frequency for series mode depends only on 
the capacitance CS1 and inductance LS1, and is given by: 
112
1
SS
OSC CL
f
SERIES �
� (3) 
The oscillation frequency for parallel mode is affected by 
the parallel crystal capacitance (C0) and the load capacitance 
associated with the feedback network. It can be expressed by: 
LS
L
SS
OSC
CCC
CCCL
f
PARALELL
��
�
�
01
0
112
1
�
 
(4) 
The load capacitance (CL) is composed by the equivalent 
capacitance at the nodes 1 and 2 (C1 and C2 in series), the stray 
capacitance (CSTRAY), and the device unit inter pin-out parasitic 
capacitance (some authors also include the board inter tracks 
parasitic capacitance). Thus, CL is: 
USTRAYL CCCC ��� 12 (5) 
where C12 is given by: 
21
21
12 CC
CCC
�
� (6) 
The relationship between the parallel and series mode 
oscillation frequency is found combining Eqs. (3) and (4): 
)(
1
0
1
L
S
OSCOSC CC
Cff
SERIESPARALELL �
�� (7) 
Expression (7) shows that the parallel resonant mode occurs 
very close to the series mode oscillation frequency, ands its 
proximity is affected by the load conditions. Hence, the term 
inside the radix is very small. Some authors [5] expand this 
term in Taylor´s series disregarding high order terms, obtaining 
the following approximation: 
		
�
��
�
�
��
)(2
1
0
1
L
S
OSCOSC CC
Cff
SERIESPARALELL
 (8) 
Expression (8) is accurate enough to describe the frequency 
dependence with hundreds of ppm deviation. Now, replacing 
CL by Eq. (5), the feedback network components can be 
included as follows: 
� �	
	
�
��
�
���
��
USTRAY
S
OSCOSC CCCC
Cff
SERIESPARALELL
012
1
2
1 (9) 
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Isolating and combining all parallel components in a CP 
term, and normalizing the relation to C0 by the parameter p: 
00 )1( CpCCCC USTRAYP ����� (10) 
Eq. (8) can be defined in terms of the load components as: 
� �	
	
�
��
�
�
��
P
S
OSCOSC CC
Cff
SERIESPARALELL
12
1
2
1 (11) 
Notice the load capacitors at nodes 1 and 2 could be 
different by design imposition or mismatch. Thus, one can 
represent them by: 
12 CC �� (12) 
where � is the ratio between the capacitances. Replacing Eq. 
(12) in (6) to get C12 in terms of C1 gives: 
1
11
11
12 1
C
CC
CCC
�
�
�
�
�
�
�
� (13) 
Defining the set of capacitances associated with node 1 as 
formed by a fix part (CFIX) related to a fix capacitance, and a 
variable part CD related to reverse junction capacitances, then: 
DFIX CCC ��1 (14) 
The fix capacitance term includes the external (C1EXT), the 
internal (C1INT), and the pad capacitance (board capacitance are 
considered into external one). The relation among them can be 
normalized with regard to C0 by the ratio f, as: 
011 fCCCCC PADINTEXTFIX ���� (15) 
Note CD is related to the reverse voltage applied to the 
junctionsat the ESD protection structures located at XTAL1 
and XTAL2 I/O pins. In this analysis, a typical rail based 
connection will be considered; the diodes in reverse bias are 
connected to VDD (by PBULK) and to GND (via substrate). The 
expression for CD comes after [15] but it can be normalized to 
C0 by the factor v as given by: 
01
0
0
1
vC
V
CC
N
R
J
D �
		
�
��
�
�
�
�
 
(16) 
Replacing (15) and (13) in (16), C1 can be written in terms 
of C0 as follows: 
0111 )()( CvfCCCCC DPADINTEXT ������ (17) 
In absence of any interference (by substrate or PBULK 
potential variation due to RFI) C1 is constant and can be 
simplified defining x=(f + v), so: 
001 )( xCCvfC ��� (18) 
Hence, the capacitance between nodes 1 and 2 can now be 
given in terms of C0 as: 
012 1
xCC
�
�
�
� (19) 
Once all capacitances have been normalized in relation to 
C0, replacing (10) and (19) in (11), yields: 
	
	
	
	
�
�
�
�
�
�
��
�
��
� ��
�
��
00
1
)1(
1
2
1
CpxC
C
f
f S
OSC
OSC
SERIES
PARALELL
�
�
 
(20) 
By simple algebra, Eq. (20) can be rewriten as: 
0
1
1)1(
1
2
11
C
C
ppxf
f
S
OSC
OSC
SERIES
PARALELL
�
�
�
�
�
�
����
�
��
�
� (21) 
Eq. (21) provides the relationship between the parallel and 
series oscillation frequency regarding all network components 
parameterized to C0. From Eq. (21), one can extract a load 
factor term (LF) to concatenate all network load influence 
defined by: 
1)1(
1
2
1
����
�
�
ppx
LF �
� (22) 
where constant parameter p represents the stray and device 
capacitance, sometimes already computed in C0 by some 
manufacturers or designers. On robust designs p << 1, thus, 
with enough ppm accuracy, Eq. (22) reduces to: 
1)1(
1
2
1
��
�
�
x
LF �
� (23) 
Eq. (23) is plotted in Fig. 5 as a surface in terms of C2/C1 
ratio with node capacitance as a function of C0. Note that load 
factor have more variation for a heavy x due to large 
capacitance increments on nodes 1 or 2. C2/C1 ratio introduces 
weak variation on load factor LF. 
Finally, the relation between the Pierce´s crystal oscillation 
mode in terms of the load factor is given by: 
0
11
C
CL
f
f S
F
OSC
OSC
SERIES
PARALELL �� (24) 
Considering a typical 4MHz crystal with CS1=54fF and 
C0=2.9pF, the frequency deviation can be plotted as a surface 
function on Fig. 6. Note the function shows the same behavior 
observed in LF. Also note the load factor is obtained isolating it 
in Eq. (24) and measuring the parallel frequency to evaluate LF, 
once C0, CS1 and the series resonant frequency are specified by 
the crystal manufacturer: 
	
	
�
�
�
�
�� 1
1
0
SERIES
PARALELL
OSC
OSC
S
F f
f
C
CL (25) 
Assuming the oscillator is under RF interference but the 
average value of the substrate voltage is such that keeps the 
diodes operating in reverse bias (case A, no rectification 
phenomena in place), and considering p << 1 with � = 1, the 
load factor approximates to: 
1)1(
2
2
1
���
�
fv
LF (26) 
where v and f are the variation ratio due to RFI (from 0.01 to 
100) and the fix ratio in the crystal nodes 1 and 2 regarding C0, 
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respectively. Eq. (26) yields the surface shown in Fig. 7. �In 
this case, the frequency ratio is severely affected under strong 
RF interference because the junction capacitance ratio CJ/C0 
increase due to the reduction in the potential barrier depth. 
Observe the deviation is accentuated for high CX/C0 ratios 
(high capacitance value placed at nodes 1 and 2). 
IV. RF-FAULT INJECTION SIMULATION RESULTS 
The oscillator in Fig. 1 was simulated using a 0.35μm 
CMOS process with proper RF models for the devices and the 
substrate. A simple inverter operating in linear region was used 
as feedback amplifier. The RF interference signal was set for a 
frequency of 100MHz with a source impedance of 50� being 
coupled to substrate through ZC. The simulation bench 
considers all network elements discussed in Section II. Logic 
output drivers were also added to the test bench in order to 
analyze the RF disturbance induced at the output clock. 
Fig. 8-A illustrates the simulation results for a low power 
interference level (-10dBm). The RF interference injection 
causes noise superposition at crystal nodes 1 and 2. No 
significant disturb is observed on the crystal voltage or current 
waveform. The issue generated by the RF superposition also 
causes an induced bounce at the output driver. This behavior 
results in clock instability and jitter, making the oscillator to 
lose their precision. Observe this behavior in the zoom window 
shown in Fig. 8-B. 
 
With a higher power level (+18dBm) of RF interference 
injected to the substrate, node 1 becomes susceptible to the 
rectification mechanism until the point that the oscillation 
stops, as predicted in Case B Section II. This behavior is 
shown in Fig. 8-C and zoomed in Fig. 8-D. 
V. EXPERIMENTAL RESULTS 
The experiments reported here have been collected with a 
Pierce oscillator implemented in a 0.35μm CMOS technology. 
The circuit implementation is a typical architecture found in 
microcontrollers and has all network components integrated. 
Optional external network components can be added. Fig. 9 
shows the die photograph and layout, while Fig. 10 depicts the 
schematic including the on-chip feedback network, pad 
connections, and ESD structures. The substrate is directly 
accessed via pad. The test vehicle comprises an experimental 
stand alone crystal oscillator and some drivers to monitor the 
signals. Since the main objective is to study the interference 
effects on the oscillator block, including load impact on clock 
precision, the circuit was isolated from the MCU core and other 
Figure 8. Transient simulated behavior under several RF interference levels 
(A,B is an A-zoom) VRF = 500mV (3dBm), (C,D is a C-zoom) VRF = 2500mV 
(20dBm) @ 100MHz, Z = 50�. 
 
Figure 5. XTAL load factor function. 
 
Figure 6. Frequency deviation without interference. 
 
Figure 7. Frequency deviation with interference. 
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sub-blocks. Usually, in a complete microcontroller, besides the 
oscillator there are also several analog functions and a 
functional/test interface to share I/O pads with digital circuits 
as described in [11]. Moreover, the package also influences the 
test results, affecting mainly the behavior at higher frequencies 
due to the lead frame strays. Note some complex SoC devices 
could include an internal Analog Test Bus with RF debug and 
monitoring capabilities (ATB-RF) during the compliance tests. 
Nowadays, the ATB-RF test is done during the IC qualification 
phase but no performed in production. 
The measurement test setup in Fig. 10 details the power 
connections and the RFI injection points. To avoid RF power 
injection over the power supply, a decoupling filter is included. 
This filter adds some resonant points in the circuit, so the test 
setup must be characterized without DUT to determine its 
overall influence. Despite a clean power supply is not often 
present in a microcontroller based system, it is almost standard 
in EMC industrial compliance tests since the main goal is the 
EMC qualification. The same setup is frequently adopted for 
susceptibility debug and research. Several experiments and 
measurements can be performed with this setup. As mentioned 
before, the present work is focused in studying the interference 
effects due to RF injection on the substrate, to analyze the 
loading effects. 
Fig. 11 proposes a characterization environment for RF-
fault injection test (or EMC standard test [12]) and is more 
 
Figure 9. (A) Die photo and (B) layout of Pierce oscillatortest circuit. 
 
Figure 10. Pierce oscillator test circuit for RF fault injection analisys. 
appropriated to perform analysis in time and frequency 
domains. A DSO oscilloscope with special software performs 
behavioral and jitter analysis, while the spectrum analyzer gets 
the disturbance at the spectrum components and makes THD 
correlation. The RF power amplifier is optional depending 
upon the maximum power delivered by the RF generator. In 
EMC compliance tests, it is included a ROE power meter (not 
shown here) to check the real power delivered to DUT. Here, 
due to some equipment limitations, it was done a preliminary 
test to evaluate ROE impact. The system can be driven 
manually or automatically via GPIB. Fig. 12 shows the test 
state machine used for DPI characterization using the automatic 
option. The measurement needs some special care and attention 
regarding the RF power steps applied: in our case, each step in 
the RF power source was done to reach a desired level avoiding 
peaks in the RF generator output. Time between events should 
be adjusted considering the device and crystal overheating 
during the test to minimize temperature influence on the 
experimental results. In summary, the test is not easy and some 
experience should be needed to complete it successfully. As an 
additional setup detail, it was employed the filter option in the 
frequency counter for frequency and period capture. 
 
Figure 11. Test setup for RF fault injection analisys. 
 
Figure 12. Test state machine for DPI - RF fault injection analisys. 
 
(A) 
(B) 
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Figure 13. Transiente response for RF fault injection. 
 
 
Figure 14. (A) Evatuated percentual frequency deviation induced by RF fault 
injection regarding the change in CL capacitance; (B) Measured deviation for a 
500MHz RF fault injection 
In this way, a RF interference test compliant with [12] was 
performed on the Pierce crystal oscillator device. Fig. 13 shows 
the transient response at the oscillator output before and after 
the RF injection. Note that the RF power relay (SSR) demands 
certain time to deliver the full power to the load. Hence, the tmax 
parameter should be characterized before (as depicted by the 
RF generator sync signal in Fig. 13), to set the timing in the test 
program. 
A particular behavior with a 500MHz RF CW signal 
(frequency of maximum interference due to substrate coupling 
for this technology) is shown in Fig. 14. The power is increased 
from the linear to the non-linear region to check the oscillator 
behavior, as described in Section II. Note the frequency 
deviation found after the center of the interference (10 dBm). 
The offset in amplitude and time delay in relation to signal 
without interference were characterized too. The frequency has 
more variation (non linear behavior), then injected power 
increases confirming the prediction given by Eq. (3). 
 
 
Figure 15. DPI test result for RF injection on subatrate, (A) configuration with 
external C1 and C2 of 10pF, (B) only internal C1 and C2. 
Fig. 15 illustrates some interesting results when a frequency 
scan is done at several power levels in order to check the 
oscillator deviation in ppm. In Fig. 15(A) it was used a 
conventional Pierce oscillator configuration with external load 
capacitors (C1 and C2) of 10pF plus a stray capacitance of 8pF. 
Note the small disturbance of a few ppm in frequency, 
demonstrating the oscillator keeps its precision despite the 
strong interference level. Below 10 dBm of the injection power 
level, the results are not so precise because is not easy to isolate 
the fenomena from the the selfheating variation. However, in 
Fig. 15(B) using just the internal capacitors, the impact is more 
severe and the oscillator loses its precision. Note the large 
contrast due to the ESD loading effect and other substrate 
coupling that introduces great deviation in the oscillator output 
frequency. Finally, depending on the power level, the 
interference effect can be caused due to the loading (low level, 
lower than 10dBm) or by rectification and clock corruption 
(high level, greathet than 10dBm) as predicted in Section II. 
VI. CONCLUSIONS 
This work analyzes the impact of RF interference on 
Pierce crystal oscillator parameters such as frequency stability 
and drift, and several fault conditions in applications. A 
prediction method based on the load factor was presented and 
design guidelines were drawn to enhance circuit robustness. 
Theoretical analysis was confirmed by RF injection 
simulations. Both theory and simulation results are in good 
agreement with the experimental data. Finally, a test method 
and strategy have been suggested to perform such 
characterization via ATB-RF in complex SoC devices as 
microcontrollers, as well as for research purpose. 
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Wiley & Sons, 1983. 
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Oscillator Circuits: Theory and Application", IEEE Journal of Solid-
State Circuits, Vol. 23, No. 3, pp. 774-783, Jun. 1988 
[4] C. Cox and C. Merritt.,“ Microcontroller Oscillator Circuit Design 
Considerations”, Application Note, AN1706/D, Freescale 
Semiconductor , 2004 
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