Digital Design_ Principles and Practices, Chegg Solution Manual_parte_361

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Step 1 of 3 7.070E Master-slave flip-flops are also called as pulse triggered because they require both logic 0-to-1 and 1-to-0 transitions on the clock input for proper operation. If in a synchronous sequential circuit, a SR flip-flop is used, an unstable oscillation cannot occur because at all the times, either the master or the slave latch is in the mode hold. The master slave SR flip-flop as shown in figure 1. Master Slave S S C C R R R Q C (clock) Figure 1 Step 2 of 3 The excitation table and state diagram for the SR master-slave flip-flop are presented in figure 2(a) and figure 2(b) respectively. The columns S, R, and Q denote the conditions on the flip-flop signals before the clock pulse is applied. The Q* column denotes the flip-flop output after the clock pulse has been applied. The state diagrams of the simple SR latch and the master-slave SR latch are identical. The difference between them is that the latch changes states immediately when S or R changes, whereas all flip-flop state changes are triggered by clock pulses. 0 0 0 0 No change 0d SR 0 0 1 1 0 1 0 0 Reset 10 011 0 1 0 0 1 Set 01 1 0 1 1 (b) 1 1 0 X Not allowed 1 1 1 (a) Figure 2 Step 3 of 3 Using the transition table the excitation equation is The excitation equation is in the form Qi* = expr writing it in the form =S+R'Q = The derived excitation equaiton is same as Qi* Thus, any transititon equaton can be written as