Digital Design_ Principles and Practices, Chegg Solution Manual_parte_329

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Step 1 of 2 7.038E Whenever the setup and hold times don't meet in any flip-flop, it enters into a state where its output is unpredictable: this state is known as meta-stability. Consider a D latch and input to the D latch is obtained from the combinational circuit. Figure 1 represents occurrence of the meta-stability with being the setup time and being the hold time. output data Combinational logic clk Th Tsu data output Figure 1 Step 2 of 2 The meta-stability is reached when the flip-flop setup and hold times are violated. Assume the use of a positive edge triggered "D" flip-flop. Whenever the rising edge of the D flip-flop occurs at the time when the input to the D flip-flop causes the master latch to transition, then the flip-flop is more likely to end up in meta-stability. Thus, explained the occurrence of meta-stability in D latch.