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Step of 6 8.045E Consider a synchronous sequential circuit clocked having four inputs N3, N2, N1, which represents an integer in the range of 0-15 with single output Z having asserted to N clock ticks in the 16-tick interval. This is implemented by using free running divide by 16 counter and the ticks of Z are evenly spaced for as possible. The VHDL code for implementation of this circuit is as follows: Step 6 Step library IEEE; use 164 all; use all; entity counter is port (CLK, LD_L, ENP, ENT: in STD_LOGIC; N: in unsigned(7 downto 0); Z: out STD_LOGIC); end counter; architecture counter_arch of counter is signal IQ: unsigned(7 downto 0); begin process(CLK, ENT, IQ) begin if(CLK'event and CLK '1') then if CLR_L = then IQ elsif LD_L then IQ elsif LD_L then IQ