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Step 1 of 2 8.14DP Consider the following data: Inputs ENP, ENT, and D always HIGH Inputs A, B, C always LOW Input implies Gate NAND of outputs (QA, QC) is fed to input LD_L. Similarly implies Gate NAND of outputs (QB, QD) is fed to input The CLK input is hooked up to a free-running clock signal. Draw the 74x163 modulo-16 counter as per the data. CLOCK CLK ENP ENT D c QA B A QB QC CLR LD QD Figure 1 Step 2 of 2 The sequence starts with the state 0000 and then counts to 0001 till 0101 as shown in Table 1. Since QA and QC is fed as an input to the NAND gate, at the state 0101 the LD becomes 0 and the input is fed as the output, the state becomes 1000 when it is clocked and then counts to 1001 till 1010. Since QB and QD is fed as an input to the NAND gate, at the state 1010 the CLR becomes 0 which resets the state to 0000. The Output sequence for the circuit is shown in table 1. Table 1 QD QC QB QA 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 Thus, desired sequence is tabulated.