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Step 1 of 3 8.035E The 74x163 is a high-speed synchronous MOD-16 binary counter. This is synchronously pre-settable by LD (Parallel Enable input) for application in programmable dividers. It has two count enabler inputs such as ENP (Count Enable Parallel input) and ENT (Count Enable Trickle input). The 74163 has a Terminal Count output (RCO) to facilitate high speed synchronous counting. It has a Synchronous Reset (CLR) input that overrides counting and parallel loading and allows the outputs to be simultaneous Reset on the rising edge of the clock. Both count enables (ENP and ENT) must be HIGH to count. The terminal count output (RCO) will go HIGH when the highest count is reached. RCO will be forced LOW, however, when ENT goes LOW, even though the highest count may be reached. Step 2 of 3 Now, the count sequence is 4, 5, 6 13, 14, 4, 5, 6 It is observed that the sequence is starting from number 4. Represent this number in binary form 4 (binary 0100). The count starts from 4. Therefore, for count to start from 4 (binary 0100) we have to pre-load the counter with 0100 (DCBA), with LD = 0 It is also observed from the count sequence that the highest count is 14 (binary 1110). Therefore, when the count reaches 15 (binary 1111), the counter starts its counting from pre-set count that is 4 (binary 0100). The design of the counter is shown in Figure 1. 0 0 0 1 0 LD A B C D 1 ENP 1 ENT 74163 RCO Clock CLK CLR QA QB QC QD Figure 1 Step 3 of 3 Take the QA, QB, QC, and QD as outputs and connect it with the synchronous clear CLR through a NAND gate, then when the count reaches 15 (binary 1111) the (CLR) input becomes LOW (0) and the counter would RESET to 4 (binary 0100) and the counting starts from 4 (binary 0100) again.