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189
Chapter 10
Exercise 10.1 Comparison of FA implementations
(a) using a two-level network (Fig. 10.3(a) of the textbook) the critical path for the circuit has
3 gates. The path connects the input x
i
(or y
i
or c
i
) and output z
i
. The propagation delay of this
path is obtained as:
T
pHL
(x
i
! z
i
) = t
pHL
(NOT ) + t
pLH
(NAND � 3) + t
pHL
(NAND � 4)
T
pHL
(x
i
! z
i
) = 0:05 + 0:017 � 2 + 0:07 + 0:038 � 1 + 0:12 + 0:051L
T
pHL
(x
i
! z
i
) = 0:312 + 0:051L
T
pLH
(x
i
! z
i
) = t
pLH
(NOT ) + t
pHL
(NAND � 3) + t
pLH
(NAND � 4)
T
pLH
(x
i
! z
i
) = 0:02 + 0:038 � 2 + 0:09 + 0:039 � 1 + 0:10 + 0:037L
T
pLH
(x
i
! z
i
) = 0:325 + 0:037L
However, the delay of the path connecting the carry input to the carry output is also important
for carry ripple adders. This path has a worst case delay:
T
pHL
(c
i
! c
i+1
) = t
pLH
(NAND � 2) + t
pHL
(NAND � 3)
T
pHL
(c
i
! c
i+1
) = 0:05 + 0:038 + 0:09 + 0:039L
T
pHL
(c
i
! c
i+1
) = 0:18 + 0:039L
T
pLH
(c
i
! c
i+1
) = t
pHL
(NAND � 2) + t
pLH
(NAND � 3)
T
pLH
(c
i
! c
i+1
) = 0:08 + 0:027 + 0:07 + 0:038L
T
pLH
(c
i
! c
i+1
) = 0:18 + 0:038L
The number of equivalent gates is:
gate type number of gates equivalent gates
NOT 3 3� 1 = 3
NAND-3 5 5� 2=10
NAND-2 3 3� 1=3
NAND-4 1 1� 2 = 2
Total 18
(b) using HA (Fig. 10.3(b) of the textbook)
The critical path for this circuit has 3 gates: XOR-2, AND-2 and OR-2. The path connects the
input x
i
(or y
i
) and output c
i+1
. The propagation delay of this path is obtained as:
T
pHL
(x
i
! c
i+1
) = t
pHL
(XOR � 2) + t
pHL
(AND � 2) + t
pHL
(OR� 2)
T
pHL
(x
i
! c
i+1
) = 0:3 + 0:021 � 3 + 0:16 + 0:017 + 0:2 + 0:019L
T
pHL
(x
i
! c
i+1
) = 0:74 + 0:019L
T
pLH
(x
i
! c
i+1
) = t
pLH
(XOR � 2) + t
pLH
(AND � 2) + t
pLH
(OR� 2)
T
pLH
(x
i
! c
i+1
) = 0:3 + 0:036 � 3 + 0:15 + 0:037 + 0:12 + 0:037L
T
pLH
(x
i
! c
i+1
) = 0:72 + 0:037L
The number of equivalent gates is:
190 Solutions Manual - Introduction to Digital Design - June 3, 1999
gate type number of gates equivalent gates
XOR-2 2 2� 3 = 6
AND-2 2 2� 2=4
OR-2 1 1� 2=2
Total 12
(c) using XOR and NAND gates (Fig. 10.3(c) of the textbook)
As the NAND gates have smaller propagation delays than XOR gates, the critical path for
this circuit is through the 2 XOR gates. The path connects the input x
i
(or y
i
) and output z
i
.
Observe that when the �rst XOR gate is connected to the input with higher load factor of the
second XOR gate, the delay of the second XOR gate is reduced. So, two cases must be considered.
The propagation delay of this path is obtained as:
T
pLH
(x
i
! z
i
) = t
pLH
(XOR � 2) + t
pLH
(XOR � 2)
T
pLH
(x
i
! z
i
) = max(0:3 + 0:036 � 3 + 0:16 + 0:036L; 0:3 + 0:036 � 2:1 + 0:3 + 0:036L)
T
pLH
(x
i
! z
i
) = max(0:568 + 0:036L; 0:6756 + 0:036L)
T
pLH
(x
i
! z
i
) = 0:68 + 0:036L
T
pHL
(x
i
! z
i
) = t
pLH
(XOR � 2) + t
pHL
(XOR � 2)
T
pHL
(x
i
! z
i
) = max(0:3 + 0:036 � 3 + 0:15 + 0:020L; 0:3 + 0:036 � 2:1 + 0:3 + 0:021L)
T
pHL
(x
i
! z
i
) = max(0:558 + 0:02L; 0:6756 + 0:021L)
T
pHL
(x
i
! z
i
) = 0:68 + 0:021L
The carry output propagation delay is:
T
pLH
(c
i
! c
i+1
) = t
pHL
(NAND � 2) + t
pLH
(NAND � 2)
T
pLH
(c
i
! c
i+1
) = 0:08 + 0:027 + 0:05 + 0:038 � L
T
pLH
(c
i
! c
i+1
) = 0:16 + 0:038L
T
pHL
(c
i
! c
i+1
) = t
pLH
(NAND � 2) + t
pHL
(NAND � 2)
T
pHL
(c
i
! c
i+1
) = 0:05 + 0:038 + 0:08 + 0:027L
T
pHL
(c
i
! c
i+1
) = 0:17 + 0:027L
The number of equivalent gates is:
gate type number of gates equivalent gates
XOR-2 2 2� 3 = 6
AND-2 3 3� 1=3
Total 9
This last implementation is the one with the least number of gates. It also has less propagation
delay for the carry than case (a).
Exercise 10.2 Analysis of a 4-bit binary Carry Ripple Adder using the HA implementation
with NANDs presented in Figure 10.3c of the textbook, each FA has 3 NAND-2 and 2 XOR-2
gates. Given the number of equivalent gates of the NAND-2 (1) and XOR-2 (3), the FA has a size
of 9 equivalent gates, and the 4-bit CRA has size 4� 9 = 36 equivalent gates.
The input load factors for the FA are:
Solutions Manual - Introduction to Digital Design - June 3, 1999 191
Input load factor
Input load
x
i
2.1
y
i
3
c
i
3
where we assume that the XOR input with highest load (2) is used for y
i
and c
i
.
The worst case delay is given in the book (page 281) as:
t
p
= t
XOR
+ 2(n� 1)t
NAND
+max(2t
NAND
; t
XOR
)
Two NAND gates in series have a delay:
t
pLH
(NAND �NAND) = 0:08 + 0:027 + 0:05 + 0:038L = 0:16 + 0:038L
t
pHL
(NAND �NAND) = 0:05 + 0:038 + 0:08 + 0:027L = 0:17 + 0:027L
and since c
in
is connected to the XOR input with L = 2, the XOR delay is:
t
pLH
(XOR � 2) = 0:16 + 0:036L
t
pHL
(XOR � 2) = 0:15 + 0:020L
Since the XOR gate may complement or not its input; any type of input transition may cause
a desired output transition. The worst delay of the series of NAND gates is for LH transition. In
this case, the critical path for each type of transition is:
� LH transition: XOR-2 ! 4 two NAND-2 ! XOR-2
� HL transition: XOR-2 ! 5 two NAND-2
and the delays are:
T
pLH
(x
0
! z
3
) = 0:3 + 0:021 � 2:1 + 3� (0:168 + 0:027 � 3) + 0:16 + 0:036L
T
pLH
(x
0
! z
3
) = 1:25 + 0:036L
T
pHL
(x
0
! c
4
) = 0:3 + 0:021 � 2:1 + 3� (0:168 + 0:027 � 3) + 0:17 + 0:027L
T
pHL
(x
0
! c
4
) = 1:26 + 0:027L
Analysis of the 4-bit Carry Look-ahead Adder (Figure 10.5 from the textbook):
In order to have a fair comparison, we replace the AND-OR network inside the CLG by a
NAND-NAND network. No decomposition into smaller gates is necessary since NANDs with 5
inputs are available on Table 4.1 of the textbook.
The network size of the CLA when using NAND gates inside the CLG is:
Gate type Number Eq. gate Size
XOR2 8 3 24
AND2 4 2 8
NAND2 5 1 5
NAND3 4 2 8
NAND4 3 2 9
NAND5 2 4 8
OR4 1 3 3
AND4 1 3 3
Total 68
192 Solutions Manual - Introduction to Digital Design - June 3, 1999
For the delay we examine two possibilities:
� Option 1:
t
pLH
(x
0
! c
4
) = t
pLH
(XOR2) + t
pHL
(NAND5) + t
pLH
(NAND5)
t
pLH
(x
0
! c
4
) = 0:3 + 0:036 � 5:1 + 0:34 + 0:019 + 0:21 + 0:038L = 1:05 + 0:038L
t
pHL
(x
0
! c
4
) = t
pHL
(XOR2) + t
pLH
(NAND5) + t
pHL
(NAND5)
t
pHL
(x
0
! c
4
) = 0:3 + 0:021 � 5:1 + 0:21 + 0:038 + 0:34 + 0:019L = 1:00 + 0:019L
� Option 2:
t
pLH
(x
0
! z
3
) = maxft
pLH
(XOR2) + t
pHL
(NAND4) + t
pLH
(NAND4); t
pHL
(XOR2) +
t
pLH
(NAND4) + t
pHL
(NAND4)g + 0:16 + 0:036L
t
pLH
(x
0
! z
3
) = maxf0:3 + 0:036 � 5:1 + 0:12 + 0:051 + 0:10 + 0:037 � 2;
0:3 + 0:021 � 5:1 + 0:10 + 0:037 + 0:12 + 0:051 � 2g+ 0:16 + 0:036L
t
pLH
(x
0
! z
3
) = maxf0:66; 0:77g + 0:16 + 0:036L
t
pLH
(x
0
! z
3
) = 0:93 +0:036L
t
pHL
(x
0
! z
3
) = maxf: : :g+ 0:15 + 0:020L
t
pHL
(x
0
! z
3
) = 0:77 + 0:15 + 0:020L = 0:92 + 0:020L
From these equations we determine the network delay taking the largest values for LH and HL
transitions from both options:
t
pLH
(x
0
! c
4
) = 1:05 + 0:038L
t
pHL
(x
0
! c
4
) = 1:00 + 0:019L
From these �gures we conclude that the CLA adder uses more gates than the ripple carry adder
but has a smaller propagation delay.
Exercise 10.3 The BCD to Excess-3 converter using 4-bit binary adder is shown in Figure 10.1.
Exercise 10.4 BCD Addition
When we add two BCD digits (0..9), considering a carry-in bit, the range of values obtained is
from 0 to 19. The output consists of a carry out and a digit coded in BCD also.
s = (a+ b+ C
IN
) mod 10
C
OUT
=
(
1 if (a+ b+ C
IN
) � 10
0 if otherwise
where s; a and b are BCD digits.
When the integers a and b are applied to the inputs of the binary adder, the output is:
z = (a+ b+ C
IN
) mod 2
4
C
0
=
(
1 if (a+ b+ C
IN
) � 2
4
0 if otherwise
So, looking at the binary adder output and comparing to the expected output for the BCD
adder, we must consider three cases:
Solutions Manual - Introduction to Digital Design - June 3, 1999 193
Binary
Adder
0
cincout
0011
BCD
code
Excess-3
Code
not used
Figure 10.1: BCD to Excess-3 converter - Exercise 10.3
(i) C
0
= 0 and z < 10: the output of the binary adder does not need correction
(ii) 10 � z � 15 and C
0
= 0: in this case we convert the sum as follows:
s = z mod 10 = (z � 10) = (z + 6) mod 16
As the operation is done with 4 bits, adding 6 is equivalent to subtracting 10.
C
OUT
= 1
(iii) C
0
= 1: in this case z = (A + B + C
in
) � 16 and we want s = (A + B + C
in
) mod 10. For
this range of values we have (A+B + C
in
) mod 10 = (A+B + C
in
)� 10, so we make:
s = z + 6
C
OUT
= 1
Therefore, to obtain the BCD adder, the following operations must be performed to the binary
adder output (z):
s =
(
z if z � 9 and C
0
= 0
(z + 6) mod 16 if 10 � z � 15 or C
0
= 1
C
OUT
=
(
0 if z � 9 and C
0
= 0
1 if z � 10 or C
0
= 1
The condition z � 10 or C
0
= 1 is described by the switching expression:
w = (z
1
z
3
+ z
2
z
3
+ C
0
)
The circuit is shown in Figure 10.2.
Exercise 10.5: Adder of decimal digits in Excess-3 code.
194 Solutions Manual - Introduction to Digital Design - June 3, 1999
Binary
Adder
Binary
Adder
0 0
a b
s
__
_
cin
Cout
=0
0
Figure 10.2: BCD adder (Exercise 10.4)
Let a and b be the decimal digits to be added. The addition is described by:
s = (a+ b+ C
in
) mod 10
C
out
=
(
1 if (a+ b+ C
in
) � 10
0 otherwise
The relation between the Excess-3 and the binary representation of a is:
a
r
(E3 ) = a
r
(bin) + 3
where
a
r
(bin) =
3
X
i=0
a
i
(bin)2
i
a
r
(E3 ) =
3
X
i=0
a
i
(E3 )2
i
and similarly for b and s.
Consequently, the digit addition is described by the following expressions:
(a) If (a
r
(E3 ) + b
r
(E3 ) + C
in
) < 16) (that means (a+ b+ C
in
) � 9), then
s
r
(E3 ) = a
r
(E3 ) + b
r
(E3 )� 3 + C
in
and
C
out
= 0
(b) If (a
r
(E3 ) + b
r
(E3 ) +C
in
) � 16) then
s
r
(E3 ) = a
r
(E3 ) + b
r
(E3 )� 3 + C
in
� 10
Solutions Manual - Introduction to Digital Design - June 3, 1999 195
and
C
out
= 1
Now consider the implementation. If we apply a and b in E3 code to a 4-bit binary adder we
get the sum z and the carry-out bit (C
o
) as:
z = (a
r
(E3 ) + b
r
(E3 ) + C
in
) mod 16
and
C
o
= 1 if (a
r
(E3 ) + b
r
(E3 ) +C
in
) � 16
Comparing the expressions for (s
r
; C
out
) and (z; C
o
) we get:
s
r
(E3 ) =
(
z � 3 if C
o
= 0
z + 3 if C
o
= 1
C
out
= C
o
and since z � 3 = (z + 13) mod 16, we obtain the network of Figure 10.3, on page 195.
Binary Adder
Binary Adder
ba_ _
z_
CinCout
s
44
4
4
_
Excess-3 adder
Figure 10.3: Excess-3 adder - Exercise 10.5
Exercise 10.6 The connection between the decoder and the encoder implies:
w = (a; b; c) = (x+ 2) mod 8
Considering x and y the integers represented by (x
2
; x
1
; x
0
) and (y
2
; y
1
; y
0
), respectively, the
output of the adder is:
z = (w + y) mod 8
and substituting w, we get:
z = (x+ y + 2) mod 8
196 Solutions Manual - Introduction to Digital Design - June 3, 1999
The switching functions can be obtained introducing the appropriate codes for variables x and
y, and specifying the functions by means of tables or expressions. This process is straighforward.
However, the obtained high-level description indicates that the system can be implemented with
two 3-bit adders to add up x, y, and 2 in modulo 8. The value An equivalent network with fewer
modules is shown in Figure 10.4.
Binary
ADDER
x2 x1 x0
0cin
y2 y1 y0
Binary
ADDER
0cin
z2 z1 z0
0 1 0
Figure 10.4: Exercise 10.6
Exercise 10.7
Input: A;B 2 f0; 1; 2; 3g and C
in
2 f0; 1g
Output: Z 2 f0; 1; 2; 3g and C
out
2 f0; 1g
Function:
Z = (A+B + C
in
) mod 4
C
out
=
(
1 if (A+B + C
in
) � 4
0 otherwise
A function table is shown in Table 10.1.
The Kmaps for the cases c
in
= 0 and c
in
= 1 are shown next:
c
in
= 0
C
out
:
0 0 0 0
0 0 1 0
0 1 1 1
0 0 1 1
b
0
b
1
a
0
a
1
�
�
�
�
�
�
�
�
z
1
:
0 0 1 1
0 1 0 1
1 0 1 0
1 1 0 0
b
0
b
1
a
0
a
1
�
�
�
�
�
�
�
�
�
�
�
�
z
0
:
0 1 1 0
1 0 0 1
1 0 0 1
0 1 1 0
b
0
b
1
a
0
a
1
��
��
�
�
�
�
Solutions Manual - Introduction to Digital Design - June 3, 1999 197
Inputs Outputs
i C
in
a
1
a0 b
1
b
0
C
out
z
1
z
0
0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 1
2 0 0 0 1 0 0 1 0
3 0 0 0 1 1 0 1 1
4 0 0 1 0 0 0 0 1
5 0 0 1 0 1 0 1 0
6 0 0 1 1 0 0 1 1
7 0 0 1 1 1 1 0 0
8 0 1 0 0 0 0 1 0
9 0 1 0 0 1 0 1 1
10 0 1 0 1 0 1 0 0
11 0 1 0 1 1 1 0 1
12 0 1 1 0 0 0 1 1
13 0 1 1 0 1 1 0 0
14 0 1 1 1 0 1 0 1
15 0 1 1 1 1 1 1 0
16 1 0 0 0 0 0 0 1
17 1 0 0 0 1 0 1 0
18 1 0 0 1 0 0 1 1
19 1 0 0 1 1 1 0 0
20 1 0 1 0 0 0 1 0
21 1 0 1 0 1 0 1 1
22 1 0 1 1 0 1 0 0
23 1 0 1 1 1 1 0 1
24 1 1 0 0 0 0 1 1
25 1 1 0 0 1 1 0 0
26 1 1 0 1 0 1 0 1
27 1 1 0 1 1 1 1 0
28 1 1 1 0 0 1 0 0
29 1 1 1 0 1 1 0 1
30 1 1 1 1 0 1 1 0
31 1 1 1 1 1 1 1 1
Table 10.1: Function table of a 2-bit adder
198 Solutions Manual - Introduction to Digital Design - June 3, 1999
c
in
= 1
C
out
:
0 0 1 0
0 0 1 1
1 1 1 1
0 1 1 1
b
0
b
1
a
0
a
1
�
�
�
�
�
�
�
�
�
�
�
�
�
�
�
�
z
1
:
0 1 0 1
1 1 0 0
0 0 1 1
1 0 1 0
b
0
b
1
a
0
a
1
�
�
�
�
�
�
�
�
�
�
�
�
z
0
:
1 0 0 1
0 1 1 0
0 1 1 0
1 0 0 1
b
0
b
1
a
0
a
1
��
��
�
�
�
�
The following logic expressionsare obtained from the K-maps.
C
out
= (a
1
b
1
+ a
1
a
0
b
0
+ a
0
b
1
b
0
)c
0
in
+ (a
1
b
1
+ a
0
b
1
+ a
1
b
0
+ b
1
b
0
+ a
1
a
0
)c
in
z
1
= (b
1
b
0
0
a
0
1
+ a
0
1
a
0
0
b
1
+ a
1
a
0
b
1
b
0
+ a
0
1
a
0
b
0
1
b
0
+ a
1
a
0
0
b
0
1
+ a
1
b
0
1
b
0
0
)c
0
in
+(a
0
1
a
0
0
b
1
b
0
0
+ a
1
a
0
0
b
0
1
b
0
0
+ a
1
b
1
b
0
+ a
1
a
0
b
1
+ a
0
1
a
0
b
0
1
+ a
0
1
b
0
1
b
0
)c
in
z
0
= (a
0
0
b
0
+ a
0
b
0
0
)c
0
in
+ (a
0
b
0
+ a
0
0
b
0
0
)c
in
Using boolean algebra we reduce the expressions to:
C
out
= a
1
b
1
+ a
0
b
1
b
0
+ a
1
a
0
b
0
+ c
in
b
1
b
0
+ c
in
a
0
b
1
+ c
in
a
1
a
0
+ c
in
a
1
b
0
z
1
= a
0
1
a
0
0
b
1
b
0
0
+ a
0
1
a
0
b
0
1
b
0
+ a
1
a
0
b
1
b
0
+ a
1
a
0
0
b
0
1
b
0
0
+ c
in
a
0
1
b
0
1
b
0
+ c
in
a
0
1
a
0
b
0
1
+ c
in
a
1
a
0
b
1
+ c
in
a
1
b
1
b
0
+ c
0
in
a
0
1
a
0
0
b
1
+ c
0
in
a
0
1
b
1
b
0
0
+ c
0
in
a
1
b
0
1
b
0
0
+ c
0
in
a
1
a
0
0
b
0
1
z
0
= c
in
a
0
0
b
0
0
+ c
in
a
0
b
0
+ c
0
in
a
0
b
0
0
+ c
0
in
a
0
0
b
0
From the equations, we count 26 NAND gates, with a maximum fan-in of 12 inputs. We assume
that NOT gates are used to obtain the complement of the input variables, so 5 NOT gates are also
used in the network. The network has one level of NOT gates, and two levels of NAND gates.
Internally, all NAND gates in the intermediate level are connected to only one input of the next
level, all loads are 1. The loads of the input signals and their complements (generated by the NOT
gates) are:
Signal Load
a
1
11
a
0
1
6
b
1
11
b
0
1
6
a
0
11
a
0
0
6
b
0
11
b
0
0
6
c 11
c
0
6
Solutions Manual - Introduction to Digital Design - June 3, 1999 199
Exercise 10.8 Design of a 6-bit CLA adder using gates with a maximum of 4 inputs. The
section that generates propagate and generate signals doesn't need gates with more than 2 inputs.
The same for the last layer of XOR gates that generates the �nal sum. The highest fan-in is required
by the gates inside the CLG module. The expressions for the CLG outputs are:
c
6
= g
5
+ p
5
g
4
+ p
5
p
4
g
3
+ p
5
p
4
p
3
g
2
+ p
5
p
4
p
3
p
2
g
1
+ p
5
p
4
p
3
p
2
p
1
g
0
+ p
5
p
4
p
3
p
2
p
1
p
0
c
0
c
5
= g
4
+ p
4
g
3
+ p
4
p
3
g
2
+ p
4
p
3
p
2
g
1
+ p
4
p
3
p
2
p
1
g
0
+ p
4
p
3
p
2
p
1
p
0
c
0
c
4
= g
3
+ p
3
g
2
+ p
3
p
2
g
1
+ p
3
p
2
p
1
g
0
+ p
3
p
2
p
1
p
0
c
0
c
3
= g
2
+ p
2
g
1
+ p
2
p
1
g
0
+ p
2
p
1
p
0
c
0
c
2
= g
1
+ p
1
g
0
+ p
1
p
0
c
0
c
1
= g
0
+ p
0
c
0
P = p
5
p
4
p
3
p
2
p
1
p
0
G = g
5
+ p
5
g
4
+ p
5
p
4
g
3
+ p
5
p
4
p
3
g
2
+ p
5
p
4
p
3
p
2
g
1
+ p
5
p
4
p
3
p
2
p
1
g
0
From these expressions we observe that AND and OR gates with 5, 6 and 7 inputs are required.
We decompose these gates into three gates. The implementation of the 6-bit CLA is shown in
Figure 10.5. From the Figure we count 66 gates distributed in 6 levels.
c0
x0y0
p0g0
x1y1
p1g1
x2y2
p2g2
x3
y3
p3g3
x4y4
p4g4
x5y5
p5g5
c1c2
c3
c4c5c6 p5
s5
p4
s4
p3
s3
p2
s2
p1
s1 s0
p0
c0
G
P
Figure 10.5: 6-bit CLA using gates of at most 4 inputs - Exercise 10.8
Exercise 10.9 Design of 64-bit adders.
a) a Ripple Carry Adder (RCA) using 4-bit adder modules is shown in Figure 10.6. This
implementation of a 64-bit adder needs 16 adder modules (CLA-4). The delay is:
T
CRA
= �
CLA�xy�c4
+ 14 � �
CLA�c0�c4
+maxf�
CLA�c0�c4
; �
CLA�c0�s3
g
where �
CLA�xy�c4
is the delay to propagate the signal from input to the carry output of the 4-bit
CLA, and �
CLA�c0�c4
and �
CLA�c0�s3
are the delays from the input c
0
to the carry out c
4
and the
sum output bit s
3
, respectively.
200 Solutions Manual - Introduction to Digital Design - June 3, 1999
cincout 4-bit adder
4
4 4
4-bit adder
4
4 4
4-bit adder
4
4 4
0115
x_y_ x_ x_y_ y_ 01 1 01515
z z z___ 0115
Figure 10.6: Carry Ripple Adder (CRA) - Exercise 10.9
Based on a NAND-NAND implementation of the 4-bit CLG that is part of the 4-bit CLA we
obtain:
�
CLA�xy�c4
= t
LH
(XOR � 2) + t
HL
(NAND � 5) + t
LH
(NAND � 5)
= 0:30 + 0:036 � 5:1 + 0:34 + 0:019 � 1 + 0:21 + 0:038L
= 1:05 + 0:038L
�
CLA�c0�s3
= t
LH
(XOR � 2) + t
HL
(NAND � 4) + t
LH
(NAND � 4)
= 0:3 + 0:036L + 0:21 + 0:038 � 1 + 0:34 + 0:019 � 2
= 0:93 + 0:036L
�
CLA�c0�c4
= t
HL
(NAND � 5) + t
LH
(NAND � 5)
= 0:21 + 0:038 � 1 + 0:34 + 0:019L
= 0:59 + 0:019L
Based on the fact that the input load of c
0
is 4, we obtain the delay of the CRA as:
T
CRA
= 1:07 + 0:019 � 4 + 14(0:59 + 0:019 � 4) + 0:93 + 0:036L
= 11:4 + 0:036L
b) a Carry-lookahead Adder (CLA) using 4-bit carry-lookahead adder modules (CLA-4) and
4-bit carry-lookahead generator modules (CLG-4) is presented in Figure 10.7. Note that this design
is an extension of the design showed in Figure 10.8 of the textbook.
Observe from the Figure that 20 modules are necessary, 16 CLA modules and 4 CLG modules.
The delay of this adder can be calculated considering the following module delays:
�
CLA�xy�PG
= �
CLA�xy�c4
= 1:07 + 0:019L
�
CLG�pg�c4
= �
CLA�c0�c4
= 0:59 + 0:019L
�
CLG�c0�c3
= t
HL
(NAND � 4) + t
LH
(NAND � 4)
= 0:21 + 0:038 � 1 + 0:34 + 0:019L
= 0:59 + 0:019L
�
CLA�c0�s3
= t
LH
(XOR� 2) + t
HL
(NAND � 4) + t
LH
(NAND � 4)
= 0:3 + 0:036L + 0:21 + 0:038 � 1 + 0:34 + 0:019 � 2
= 0:93 + 0:036L
Solutions Manual - Introduction to Digital Design - June 3, 1999 201
The load of the p, g, and c
0
inputs of the CLG is 4.
The total delay is:
T
CLA
= �
CLA�xy�PG
+ �
CLG�pg�c4
+ 2� �
CLG�c0�c4
+ �
CLG�c0�c3
+ �
CLA�c0�s3
= 1:07 + 0:019 � 4 + 0:59 + 0:019 � 4 + 2(0:59 + 0:019 � 4) + 0:59 + 0:019 � 4
+0:93 + 0:036L
= 4:74 + 0:036L
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLG-4 CLG-4 CLG-4 CLG-4
cin
14z15
c64 c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c 8 c 4
z 13z 12z 11z 10z 9z 8z 7z 6z 5z 4z 3z 2z 1z 0z
c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c 8 c 4
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
x15y15 x14y14 x13y13 x12y12 x11y11 x10y10 x9y9 x8y8 x7y7 x6y6 x5y5 x4y4 x3y3 x2y2 x1y1 x0y0
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - -
Figure 10.7: 64-bit CLA with 1 level of CLGs - Exercise 10.9
Another approach is to use one more level of CLGs, this time to generate the carries of groups
of 16 bits. This scheme is presented in Figure 10.8. The propagation delay of this case is:
T
CLAv2
= �
CLA�xy�PG
+ �
CLG�pg�pg
+ �
CLG�pg�c3
+ �
CLG�c0�c3
+ �
CLA�c0�s3
where �
CLG�pg�pg
= �
CLA�c0�c4
= �
CLG�pg�c3
= �
CLG�c0�c3
= 0:59 + 0:019L. Thus
T
CLAv2
= 1:07 + 0:019 � 4 + 3(0:59 + 0:019 � 4) + 0:93 + 0:036L
T
CLAv2
= 4:07 + 0:036L
which results in a faster implementation of the CLA, at the cost of one extra CLG-4 module.
Exercise 10.10:
considering radix r = 2
� case (a) | two's complement, n = 7 bits; C = 2
7
� case (b) | one's complement, n = 8 bits; C = 2
8
� 1
� case (c) | two's complement, n = 5 bits; C = 2
5
� case (d) | two's complement, n = 8 bits; C = 2
8
Signed Integer - x Representation - x
R
Bit vector
(in decimal) (in decimal)
(a) -37 91 1011011
(b) -50 205 11001101
(c) -5 27 11011
(d) 9 9 00001001
202 Solutions Manual - Introduction to Digital Design - June 3, 1999
CLA-4
4 4
4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLA-4
4 4
2 4
CLG-4 CLG-4 CLG-4 CLG-4
CLG-4
2
2 2 2 2
c64 c48 c32 c16
c60 c56 c52
c48
c44 c40 c36
c32
c28 c24 c20
c16
c12 c8 c4
cin
c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c 8 c 4
x15y15 x14y14 x13y13 x12y12 x11y11 x10y10 x9y9 x8y8 x7y7 x6y6 x5y5 x4y4 x3y3 x2y2 x1y1 x0y0
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - -
14z15 z 13z 12z 11z 10z 9z 8z 7z 6z 5z 4z 3z 2z 1z 0z_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Figure 10.8: 64-bit CLA with 2 levels of CLGs - Exercise 10.9
We present now the calculations performed to obtain the numbers for the �rst row (a). These
numbers can be obtained in two di�erent ways: using expressions or manipulating the vector of
digits (or bits, if r = 2).
Using the expression for x < 0, we know that:
jxj = C � x
R
= 2
7
� x
R
= 37
So,
x
R
= 2
7
� 37 = 128 � 37 = 91
.
The vector of bits is easily obtained from this number in base 10.
Another way is to manipulated the vector of digits. As we know, for two's complement number
system, the representation of a number with a di�erent sign is obtained complementing all digits
with respect to (r � 1) (the greatest digit) and adding one. First we get the representation for jxj:
jxj = (37)
10
= 0100101
note that the number was represented using n = 7 bits.
1011010
+ 1
1011011
(10:1)
Where 1011011 = (91)
10
= x
R
.
Exercise 10.11:
Fixed-point number representation: (x
6
x
5
x
4
:x
3
x
2
x
1
x
0
)
(a) Sign-and-magnitude: the most signi�cant bit corresponds to the sign
x
max
= 011:1111 !
2
6
� 1
2
4
= 3:9375
x
min
= 111:1111 !
�(2
6
� 1)
2
4
= �3:9375
Solutions Manual - Introduction to Digital Design - June 3, 1999 203
(b) Two's Complement
x
max
= 011:1111 !
2
6
� 1
2
4
= 3:9375
x
min
= 100:0000 !
�2
7
+ 2
6
2
4
= �4:0
(c) One's Complement
x
max
= 011:1111 !
2
6
� 1
2
4
= 3:9375
x
min
= 100:0000 !
�(2
7
� 1) + 2
6
2
4
= �3:9375
Exercise 10.12: For addition we use the following table:
K
x
K
y
K
mx
c
0
x y z = x+ y c
out
= c
8
ovf zero sgn
0 0 1 0 01010011 00100111 01111010 0 0 0 0
0 0 1 0 01010011 01000001 10010100 0 1 0 1
0 0 1 0 10101010 10100000 01001010 1 1 0 0
0 0 1 0 10101010 11110001 10011011 1 0 0 1
0 0 1 0 10110110 00110011 11101001 0 0 0 1
0 0 1 0 10110110 01100111 00011101 1 0 0 0
For subtraction we use the table:
K
x
K
y
K
mx
c
0
x y z = x� y c
out
= c
8
ovf zero sgn
0 1 1 1 01010011 00100111 00101100 1 0 0 0
0 1 1 1 01010011 01000001 00010010 1 0 0 0
0 1 1 1 10101010 10100000 00001010 1 0 0 0
0 1 1 1 10101010 11110001 10111001 0 0 0 1
0 1 1 1 10110110 00110011 10000011 1 0 0 1
0 1 1 1 10110110 01100111 01001111 1 1 0 0
Exercise 10.13:
(a) to show that the addition in one's complement can be performed by two steps let us consider
two numbers x and y represented by x
R
= x mod C and y
R
= y mod C, where C = 2
n
� 1. We
want to obtain s
R
= w
R
mod C, where w
R
= x
R
+ y
R
is the result of the addition, represented by
the vector w
R
= fw
n
; w
n�1
; : : : ; w
1
; w
0
). The most signi�cant bit of w
R
is the carry out bit of the
n�bit addition performed with x
R
and y
R
. Since x
R
; y
R
< C, w
R
< 2C. We must consider the
following 3 cases:
1. If w
R
< C then w
R
mod C = w
R
and w
n
= 0
2. If w
R
= C then w
R
mod C = 0 and w
n
= 0
204 Solutions Manual - Introduction to Digital Design - June 3, 1999
3. If 2C > w
R
> C then w
R
mod C = w
R
� C = w
R
� 2
n
+ 1 and w
n
= 1
Consequently, if w
n
= 0, the result is equal to w
R
, and if w
n
= 1 the result is obtained discarding
w
n
(subtracting 2
n
) and adding 1. Note that case (2) produces a result vector (1; 1; : : : ; 1), which
is correct since this is another representation of 0 in the one's complement system.
(b) To verify that the operation of the adder with the carry output connected to the carry-in
is combinational we consider the following cases:
� there is a combination 00 or 11 for one particular bit position. In that case the carry chain
is broken by this combination. No active loop.
� there is no combination 00 or 11, that means, all bit positions have the combination 01. In
that case, there is an active loop. To have a stable result all carries have to be reset to zero
before the operation starts.
Figure 10.9 shows examples of both cases.
011011010
100110101
ppppgpppp
011001010
100110101
111111110
+
= cin1cout
1
spureous carry!
011001010
100110101
111101111
c
0
0
Some position with 00 or 11
carry chain
no active loop
All positions with 01 or 10
carry bit
carry chain
active loop
Figure 10.9: Example of carry chains for One's complement adder - Exercise 10.13 (part b)
Exercise 10.14: Implementation of addition in Sign-and-magnitude with 8 bits (including the
sign bit).
The algorithm for addition z = a+ b in sign-and-magnitude representation is as follows:
Input: a represented by (a
s
; a
m
), b represented by (b
s
; b
m
).
Output: z represented by (z
s
; z
m
).
Algorithm:
IF a
s
= b
s
THEN z
m
= a
m
+ b
m
z
m
= a
m
ELSE
IF (a
m
� b
m
) THEN z
m
= a
m
� b
m;z
s
= a
s
;
ELSE z
m
= b
m
� a
m
; z
s
= b
s
;
Solutions Manual - Introduction to Digital Design - June 3, 1999 205
(a) the design using a subtractor of magnitudes, one adder/subtractor, two-muxes and gates is
shown in Figure 10.10. The di�erence in sign between the operands is detected by the XOR gate,
that controls the adder/subtractor. The magnitude subtractor is used to compare the operands,
performing the operation (a � b). The comparison result is obtained from the borrow output.
When the borrow output is 1, a < b. Using the result of this comparison, the larger magnitude
operand is routed to the �rst input of the adder/subtractor, and the smaller one to the second input
(subtraend). The output of the adder/subtractor corresponds to the magnitude part of the result.
The sign must be selected, and it must be the sign of the number with the largest absolute value.
This operation is accomplished by a multiplexer controlled by the borrow output of the magnitude
subtractor, as shown in the Figure.
Mag. Subtractor
x y
88
77
sign(x)
sign(y)
bout bin0110
Mux Mux
Adder/subtractor1-sub0-add
01
Mux
sign(y) sign(x)
sign(x+y)
x+y
a b
bout =1 if a<b
Figure 10.10: SM Adder - Exercise 10.14 (part a)
(b) the design with conversion of the SM number to two's complement, operation in two's
complement system, and conversion back to SM system is shown in Figure 10.11. The conversion
from SM to two's complement is done as follows, considering x = (x
n
; x
n�1
; : : : ; x
1
; x
0
) as the SM
representation of an operand (x
n
is the sign) and z its 2's complement representation:
z =
(
(0; x
n�1
; : : : ; x
1
; x
0
) if x
n
= 0
(1; x
0
n�1
; : : : ; x
0
1
; x
0
0
) + 1 if x
n
= 1
The conversion from two's complement to SM is done as follows:
x =
(
(0; z
n�1
; : : : ; z
1
; z
0
) if z
n
= 0
(1; (z
0
n�1
; : : : ; z
0
1
; z
0
0
) + 1) if z
n
= 1
The complementer and incrementer shown in the Figure are controlled by the sign bit of the numbers
being converted.
A better implementation would just complement one of the operands when the signs are di�er-
ent. This single complementation can be done by bit-invert and carry-in forced to 1 in the adder,
as shown in Figure 10.12.
Exercise 10.15: Consider the following table for the most signi�cant bits of the operands a
n�1
and b
n�1
and the sum bit s
n�1
, during the addition of n-bit two's complement operands a and b.:
206 Solutions Manual - Introduction to Digital Design - June 3, 1999
Bit complementer
Incrementer
Adder
x
7
sign(x)
0
8
8
Bit complementer
Incrementer
y
7
sign(y)
0
8
8
Bit complementer
Incrementer
7
sign 8
7
7
8
x+y
0
Figure 10.11: SM Adder - Exercise 10.14 (part b)
a
n�1
b
n�1
s
n�1
c
n
c
n�1
Ovf
0 0 0 0 0 No
0 0 1 1 0 Yes
0 1 0 1 1 No
0 1 1 0 0 No
1 0 0 1 1 No
1 0 1 0 0 No
1 1 0 0 1 Yes
1 1 1 1 1 No
From the table one can see that the over
ow cases are related to the cases when c
n
� c
n�1
= 1.
For the one's complement system the test doesn't work properly in the case of adding (�0) +
(�2
n�1
+ 1), which corresponds to the addition of the vectors (111 : : : 11) and (100 : : : 00). If the
addition is performed in two stages (no end-around-carry), the �rst stage will generate c
n
= 1 and
c
n�1
= 0, detecting an over
ow condition that does not exist.
Exercise 10.16:
The range extension of x = (x
n�1
; : : : ; x
1
; x
0
) is represented as z = (z
m�1
; : : : ; z
1
; z
0
), with
n < m, such that:
z
i
=
(
x
n�1
for i = m� 1; : : : ; n
x
i
for i = n� 1; : : : ; 1; 0
To show the correctness of this implementation let us de�ne:
z = z
R
mod C
z
x = x
R
mod C
x
Solutions Manual - Introduction to Digital Design - June 3, 1999 207
Bit complementer
Adder
x
7
sign(x)
0
8
8
Bit complementer
y
7
sign(y)
0
8
8
Bit complementer
Incrementer
7
sign 8
7
7
8
x+y
dif
dif
Figure 10.12: Another solution for SM Adder - Exercise 10.14 (part b)
There are two possible cases:
1. if x � 0 the most signi�cant bit is zero, x
n�1
= 0, and z
R
= x
R
, thus the algorithm is correct.
2. if x < 0 the following holds:
z
R
= C
z
� jxj
x
R
= C
x
� jxj
Consequently, z
R
= C
z
� C
x
+ x
r
.
From the de�nition of C
z
and C
x
we get:
C
z
� C
x
= 2
m
� 2
n
and the value of the extended range z
R
should be:
z
R
= 2
m
� 2
n
+ x
R
From this last equation we get the following vector:
(1; 1; : : : ; 1; x
n�1
; : : : ; x
0
)
with (m� n) 1s to the left of vector x, which shows the correctness of the algorithm.
Exercise 10.17: A 4-bit ALU for ADD and NAND operations is shown in Figure 10.13. A
carry-ripple adder was implemented. By the use of a multiplexer, the output of the adder, or the
NAND gate is selected as circuit output.
208 Solutions Manual - Introduction to Digital Design - June 3, 1999
Mux
1 0
xi yi
M
ADD/NAND
cin
cout
zi
M M M M
x3 y3 x2 y2 x1 y1 x0 y0
z3 z2 z1 z0
cincout
f=ADD/NAND
Figure 10.13: 4-bit ALU for ADD/NAND
Exercise 10.18: The analysis follows the inverse path of the description given on page 300 of
the text. First, from the network, we obtain the switching expressions. Then, using the encoding
given there, we obtain the high-level description. As an intermediate step we could produce the
following Table:
Position i
3 2 1 0 output relation
S - - - S x < y
G - - - G x > y
E S - - S x < y
E G - - G x > y
E E S - S x < y
E E G - G x > y
E E E S S x < y
E E E G G x > y
E E E E depends on c
in
x = y
The G, E, and S conditions are mutually exclusive.
Exercise 10.19: Figure 10.14 shows the iterative structure to be designed. Each cell has one
bit of each of the operands (a
i
and b
i
), one carry-in (CIN), and one carry-out (COUT ). These
carries have three values: Equal, Greater, and Smaller. The comparator output is obtained from
the carry-out of the last cell. The high-level description of the cell is:
COUT =
8
>
<
>
:
CIN if a
i
= b
i
GREATER if ((a
i
> b
i
) and CIN = EQUAL) or (CIN = GREATER)
SMALLER if ((a
i
< b
i
) and CIN = EQUAL) or (CIN = SMALLER)
with the initial condition CIN = EQUAL (applied to the leftmost cell).
Considering the following encoding:
Solutions Manual - Introduction to Digital Design - June 3, 1999 209
ca
rr
y-
in Iterative
Bit
Comparator
carry-out
a n-1 b n-1
ca
rr
y-
in Iterative
Bit
Comparator
carry-out
a 1 b 1
ca
rr
y-
in Iterative
Bit
Comparator
carry-out
a 0 b 0
COMPARATOR
OUTPUT
0
0
Figure 10.14: Iterative network to compare two numbers - Exercise 10.19
Condition Code
EQUAL 00
SMALLER 01
GREATER 10
the implementation of each module is done as a combinational circuit that has the following switch-
ing function table:
a
i
b
i
CIN
1
CIN
0
COUT
1
COUT
0
0000 00
0001 01
0010 10
0011 {
0100 01
0101 01
0110 10
0111 {
1000 10
1001 01
1010 10
1011 {
1100 {
1101 {
1110 {
1111 {
Observe that the code 11 is a don't care condition.
Based on K-maps for each COUT
1
and COUT
0
we get the expressions:
COUT1
= CIN
1
+ a
i
CIN
0
0
COUT
0
= CIN
0
+ b
i
CIN
0
1
These expressions are easily implemented by gate networks.
Exercise 10.20: The network that sorts two non-negative numbers a and b is shown in Fig-
ure 10.15. The sorting order is such that z
1
� z
0
.
The output of the circuit for di�erent conditions of a and b is shown in the next table.
210 Solutions Manual - Introduction to Digital Design - June 3, 1999
MUX
0 1
s
z1
a b
A B
A>B A=B A<B
Comparator MUX
0 1
s
z0
SEL
Figure 10.15: Circuit to sort two non-negative numbers
Input condition SEL OUTPUT (z
1
; z
0
)
a < b 0 (a; b)
a = b 0 (a; b)
a > b 1 (b; a)
Exercise 10.21: A tree of 4-bit comparators implementing a 32-bit comparator is shown in
Figure 10.16, where A
(i)
= (a
4i+3
; a
4i+2
; a
4i+1
; a
4i
) and B
(i)
= (b
4i+3
; b
4i+2
; b
4i+1
; b
4i
). The equality
among inputs is implied when both G and S conditions are zeros.
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
G E S
4-bit comparator
A B
0 0 0 0
cin inputs are zeroes
for all modules
A B(7) (7) A B(6) (6) A B(5) (5) A B(4) (4) A B(3) (3) A B(2) (2) A B(1) (1) A B(0) (0)
G signals
S signals
G signals
S signals
Figure 10.16: 32-bit comparator - Exercise 10.21
Exercise 10.22: The values of the outputs are shown in Figure 10.17.
Solutions Manual - Introduction to Digital Design - June 3, 1999 211
0
1
2
3
4
5
6
7
2 1 0 2 1 0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
M
UX
D
EM
UX
ADDER
PR
IO
RI
TY
EN
CO
DE
R
0
1
2
(high)
0
0
1
0
1
1
0
1
1 1 1
a
b
c
d e f
carry_out carry-in
g
0
1
0
1
0 1 0
1
0
0
1
0
0
0
0
0
Figure 10.17: Exercise 10.22
Exercise 10.23: The values of the outputs of each module in the array multiplier is shown in
Figure 10.18.
Exercise 10.24 The implementation of the 8�4-bit multiplier is shown in Figure 10.19.
2
1
2
S
o
l
u
t
i
o
n
s
M
a
n
u
a
l
-
I
n
t
r
o
d
u
c
t
i
o
n
t
o
D
i
g
i
t
a
l
D
e
s
i
g
n
-
J
u
n
e
3
,
1
9
9
9
(a)
(b)
y 2
x7 x6 x5 x4 x3 x 2 x1 x0
y0
y1
MH MF MF MF MF MF MF MH
MF MF MF MF MF MF MF MH
MF MF MF MF MF MF MF MH
MF MF MF MF MF MF MF MH
MF MF MF MF MF MF MF MH
y3
y4
y5
p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0p13
Module MF
sum_out
Full
Adder c_in
c_out
x_bit
y_bitsum_in
Module MH
sum_out
Half
Adder
c_out
x_bit
y_bitsum_in
sum_out
Half
Adder c_in
c_out
x_bit
y_bit
OR
=1 =0 =1 =1 =0 =0 =1 =1
=1
=0
=0
=1
=1
=1
1
1
0
01 0 1 1
0 0 1 1110011
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0 1 00
10
00
01
0
1
0
0
00
1
0
0
1
1
0
011
0
01
0
00
0
11
0
0
0
00
0
1
0
1
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1 1
1
1
1
0
1
0
1
1
1
0
1
1
1
0
1
1
0
11
0
111
0
0
0
01
0
1
1
010
1
00
1
1
111
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
1
0
F
i
g
u
r
e
1
0
.
1
8
:
E
x
e
r
c
i
s
e
1
0
.
2
3
Solutions Manual - Introduction to Digital Design - June 3, 1999 213
4-bit Binary adder cincout
a3 a2 a1 a0 b3 b2 b1 b0
s3 s2 s1 s0
4-bit Binary adder cincout
a3 a2 a1 a0 b3 b2 b1 b0
s3 s2 s1 s0
4-bit Binary adder cincout
a3 a2 a1 a0 b3 b2 b1 b0
s3 s2 s1 s0
4-bit Binary adder cincout
a3 a2 a1 a0 b3 b2 b1 b0
s3 s2 s1 s0
4-bit Binary adder cincout
a3 a2 a1 a0 b3 b2 b1 b0
s3 s2 s1 s0
0
0
0
4-bit Binary adder cincout
a3 a2 a1 a0 b3 b2 b1 b0
s3 s2 s1 s0
x1
x2
x3
z0z1z2z3z4z5z6z7z8z9z10
y4 y3 y2 y1 y0
y3 y2 y1 y0
y7 y6 y5
y7 y6 y5 y4
0
y3 y2 y1 y0y7 y6 y5 y4
y3 y2 y1 y0y7 y6 y5 y4
z11
x0
Figure 10.19: 8�4-bit multiplier - Exercise 10.24Perguntas relacionadas
