Chegg Solutions for Microelectronic Circuits (Adel S Sedra, Kenneth C Smith) (Z-Library)_parte_1687

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Step of 7 15.019P consider a pseudo NMOS inverter is fabricated design process technology To design a NMOS inverter and V, are selected from process technology. Since r is being the design parameter to control the values of noise margin and select a proper value Consider the equation for (1) Step of Determine the value of r for = V Replace 1.8 V for 0.5 for V, in equation 1. I 0.1=(1.8-0.5) 1 0.1 1- r 1.3 r 0.076 1-0.076 r 1 0.924 r r=6.835 Therefore, to design a pseudo-NMOS inverter with =0.1 V select r=6.835 Step W Determine the value of Consider W L (2) W L W Replace 400- 2 for k, for k, 6.835 for r and 1 for in equation 2. L P W L W W L 6.835 W = L W =1.70 L W Therefore, the value of is 1.70 L Step Determine the low value of the noise margin 1 (3) r Replace 1.8 V for 0.5 for V, and 6.835 for r in equation 3. =0.5-(1.8-0.5) = =0.576 V Therefore, the low value of the noise margin NML 0.576 U Step Determine the dc current in the low-output state (4) Step Replace 1.8 V for 0.5 for V, for k, and for in equation 4. = Step of 7 Determine the static power (5) Replace 1.8 V for and 84.5-µA for in equation 5. 152.1 Therefore, the static power dissipation of the pseudo-NMOS inverter is 152.1