Digital Design_ Principles and Practices, Chegg Solution Manual_parte_235

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Step of 8 6.033E A possible definition of a BUT gate "Y1 if A1 and B1 are but either A2 or B2 is 0; Y2 is defined Find gate level design for the BUT gate defined, that uses minimum number of transistors when realized in CMOS. You may use inverting gates with up to inputs, AOI or OAI gates, transmission gates, or other transistor level tricks Write the output expressions (which need not be two-level sums of products), and draw the logic diagram. Step BUT gate definition: "Y1 is 1 if A1 and B1 are but either A2 or B2 is 0; Y2 is defined symmetrically." Draw the following logical diagram of BUT gate. A1 B1 A1 Y1 A2+B2 . A2 B1 A1+B1 B2 Y2 A2.B2 Figure BUT gate logical diagram Step 8 Write the expressions for the outputs of BUT Write the expression in suitable form to implement in CMOS structure Step 4 of 8 Simplify =(A1.B1)+(A2.B2) Draw the following CMOS circuit to implement B2 A1.B1 A2 Y1=(A1.B1)+(A2.B2) B1 B2 Figure 2: CMOS gate-level design circuit for Y1. Step of 8 Draw the following Logic Diagram for A1 B1 Y1=A1.B1(A2+B2) A2 B2 Figure 3: Logic Diagram for Write the expression suitable form to implement in CMOS Step Simplify Y2 further =(A2.B2)+(A1.B1) Draw the following CMOS circuit to implement Y2. A2 B2 B1 A2 B2 B1- Figure CMOS gate-level design for Y2. Step of 8 Draw the following Logic Diagram for A2 B2 A1 B1 Figure 5: Logic diagram for Y2. Logic Diagram for Step of 8 Thus, the gate level design for the BUT gate using CMOS are shown Figure 2, Figure The output expressions are The logic diagrams are shown Figure Figure