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Step 1 of 2 6.038E 4-to-16 decoder with six outputs removed is a 4-to-10 decoder without enable input. It is designed by the following logic equations. Y0=ABCD Y4=ABCD Y1=ABCD Y5=ABCD Y8=ABCD Y2=ABCD Y6=ABCD Y3=ABCD Y7=ABCD Step 2 of 2 Here Y0-8 are the outputs. The gate level diagram with A, B, C and D as inputs and Y-0 to 9 as outputs is shown in Figure 1. Y0 A Y1 Y2 Y3 B Y4 Y5 Y6 Y7 Y8 D Y9 Figure 1 The cost of such a decoder be minimized compared to 4-to-16 decoder because this is simply a 4-to-16 decoder with six outputs removed. As the number of pins is reduced, the circuit design is reduced, and thus the cost of the circuit is reduced.