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Step of 4 8.038E The 74x163 is a high-speed synchronous MOD-16 binary counter. This is synchronously pre-settable by LD (Parallel Enable input) for application in programmable dividers. It has two count enabler inputs: ENP (Count Enable Parallel input) and ENT (Count Enable Trickle input). 74x163 has a terminal Count output (RCO) to facilitate high speed synchronous counting. It has a Synchronous Reset ( CLR input that overrides counting and parallel loading and allows the outputs to be simultaneous Reset on the rising edge of the clock. Both count enables (ENP and ENT) must be HIGH to count. The terminal count output (RCO) will go HIGH when the highest count is reached. RCO will be forced LOW, however, when ENT goes LOW, even though the highest count may be reached. Step 2 of 4 The modulo-129 counter starts counting from 0, 1, 2, 3.. 128, 0, 1, and so on. 127 10 = 0111 and = 1000 0000₂ When the count reaches 128, in the next clock the count must become 0 (zero) for modulo-129 counter. Therefore, when the QC output of the second 74x163 becomes 0 from 1, then in the next clock the count must start its counting from 0. The connection arrangement for module 0-129 counter using only two 74x163 is shown in Figure 1. Clock CLK CLR 1 LD QA 1 ENT QB 1 ENP 74x163 QC A QD B RCO D CLK CLR 1 LD QA 1 ENT QB 74x163 1 ENP QC A QD B RCO C D Clock CLK CLR 1 LD QA 1 ENT QB 74x163 1 ENP QC A QD B RCO C D CLK CLR 1 LD QA 1 ENT QB 74x163 1 ENP QC A QD B RCO C D Step 3 of 4 Figure 1 Step 4 of 4 When the count reaches 127 (binary 0111 1111), in the next clock cycle the count becomes 128 (binary 1000 0000) and the QC output of the second 74x163 counter changes to 0 from 1. The QC output of the second 74x163 counter is connected to the CLR input of the both the 74x163 counter. So, when the count reaches 128, in the next clock period the count reset to 0 of both the 74x163 counter and the count starts again from 0. Thus, it is a modulo-129 counter.