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Step 1 of 1 8.052E Refer to Figure 8-36 write a VHDL code for One bit-cell of a synchronous serial counter in structural style as follows: library IEEE; use use entity one_bit_cell is port( clk, LDNOCLR, Di, NOCLRORLD, CNTENP, in bit; Qi, out bit ); end one_bit_cell; architecture Stru of one_bit_cell is component AND2 port(x,y:in bit; z:out bit); end component; component VDFFQQN port(d,clock:in bit;q,qbar:out bit); end component; component OR2 port(da,db:in bit; dz:out bit); end component; component INV port(dx:in bit;dy:out bit); end component; component NOR2 port(a,b:in bit;c:out bit); end component; component XNOR2 port(d,e:in bit); end component; signal begin A1:AND2 port A2:AND2 port A3:AND2 port map(NOCLRORLD,CDi,CDATi); XN1:XNOR2 port O1:OR2 port D1:VDFFQQN port map(DINi,clk,Qi,Q_Li); port map(CNTENi,CNTEN_Li); N1:NOR2 port map(Q_Li,CNTEN_Li); end Stru; The program has been executed in Xlinx 13.2.