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Step 1 of 1 8.053E Write a VHDL program for synchronous serial counter and provide counter size changing facility at the user end using generic statement. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use entity v74x163s is : integer := 8); --added generic port ( : in STD_LOGIC; D : in STD_LOGIC_VECTOR (n-1 downto 0); Q: out STD_LOGIC_VECTOR (n-1 downto 0); RCO: out STD_LOGIC ); end v74x163s; architecture v74x163_arch of v74x163s is component synsercell is port ( CLK, LDNOCLR, Di, NOCLRORLD, CNTENP, CNTEN : in STD_LOGIC; out STD_LOGIC ); end component; signal : STD_LOGIC; signal SCNTEN : STD_LOGIC_VECTOR (n downto 0); begin LDNOCLR