M 03 - DataSheet - TM4C123GH6PM

T iva \u2122 TM4C123GH6PM Microcontroller DA T A SHEET Copyright © 2007-2014 T exas Instruments Incorporated DS-TM4C123GH6PM-15842.2741 SPMS376E TEXAS INSTRUMENTS-PRODUCTION DA T A Copyright Copyright © 2007-2014 T exas Instruments Incorporated. T iva and TivaW are are trademarks of T exas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others. PRODUCTION DA T A information is current as of publication date. Products conform to speci\ue0bfcations per the terms of T exas Instruments standard warranty . Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability , standard warranty , and use in critical applications of T exas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. T exas Instruments Incorporated 108 W ild Basin, Suite 350 Austin, TX 78746 http://www .ti.com/tm4c http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm June 12, 2014 2 T exas Instruments-Production Data T able of Contents Revision History ............................................................................................................................. 38 About This Document .................................................................................................................... 42 Au di enc e .............................................................................................................................................. 42 Ab ou t Thi s Ma nu al ................................................................................................................................ 42 Re la ted D oc um en ts ............................................................................................................................... 42 Do cu men ta ti on C on ve nt io ns .................................................................................................................. 43 1 Architectural Overview .......................................................................................... 45 1. 1 T i va \u2122 C Se rie s Ov er vi ew .............................................................................................. 45 1. 2 TM 4C 123 GH 6P M M ic ro con tr ol le r Ov erv ie w .................................................................... 46 1. 3 TM 4C 123 GH 6P M Mi cr oc on tr oll er F eat ur es ..................................................................... 49 1. 3. 1 AR M Co rte x- M4 F Pr oc es so r Co re .................................................................................. 49 1. 3. 2 On -C hip M em or y ........................................................................................................... 51 1. 3. 3 Se ri al Co mm un ic at io ns P er iph er al s ................................................................................ 53 1. 3. 4 Sy st em In te gr at io n ........................................................................................................ 57 1. 3. 5 Ad va nce d Mo ti on C on tr ol ............................................................................................... 63 1. 3. 6 An al og .......................................................................................................................... 65 1. 3. 7 JT AG an d AR M Ser ia l Wi re D eb ug ................................................................................ 67 1. 3. 8 Pa ck agi ng a nd T em pe rat ur e .......................................................................................... 6 7 1. 4 TM 4C 123 GH 6P M M ic ro con tr ol le r Ha rdw ar e De ta il s ........................................................ 68 1. 5 Ki ts .............................................................................................................................. 68 1. 6 Su pp ort I nf or ma ti on ....................................................................................................... 68 2 The Cortex-M4F Processor ................................................................................... 69 2. 1 Bl oc k Dia gr am .............................................................................................................. 70 2. 2 Ov er vie w ...................................................................................................................... 71 2. 2. 1 Sy st em- Le ve l In te rfa ce .................................................................................................. 71 2. 2. 2 In te gra te d Co nf ig ur ab le D ebu g ...................................................................................... 71 2. 2. 3 T r ac e Po rt In te rf ac e Un it (T PI U) ..................................................................................... 72 2. 2. 4 Co rt ex- M4 F Sy st em C om po ne nt De ta il s ......................................................................... 72 2. 3 Pr og ram mi ng M od el ...................................................................................................... 73 2.3.1 Processor Mode and Privilege Levels for Software Execution .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2. 3. 2 St ac ks .......................................................................................................................... 74 2. 3. 3 Re gi ste r Ma p ................................................................................................................ 74 2. 3. 4 Re gi ste r De sc ri pt io ns .................................................................................................... 76 2. 3. 5 Ex ce pti on s an d In te rru pt s .............................................................................................. 92 2. 3. 6 Da ta T yp es ................................................................................................................... 92 2. 4 Me mo ry Mo de l .............................................................................................................. 9 2 2. 4. 1 Me mo ry Re gi on s, T y pe s an d Att ri bu te s ........................................................................... 95 2. 4. 2 Me mo ry Sy st em O rd er in g of M em ory A cc es se s .............................................................. 95 2. 4. 3 Be ha vio r of M em or y Ac ces se s ....................................................................................... 95 2. 4. 4 So ft war e Or de rin g of M emo ry A cce ss es ......................................................................... 96 2. 4. 5 Bi t- Ban di ng ................................................................................................................... 97 2. 4. 6 Da ta S tor ag e ................................................................................................................ 99 2. 4. 7 Sy nc hro ni za ti on P ri mi ti ves ........................................................................................... 10 0 2. 5 Ex ce pti on M od el ......................................................................................................... 10 1 2. 5. 1 Ex ce pti on S ta te s ......................................................................................................... 10 2 3 June 12, 2014 T exas Instruments-Production Data Tiva \u2122 TM4C123GH6PM Microcontroller 2. 5. 2 Ex ce pti on T yp es .......................................................................................................... 102 2. 5. 3 Ex ce pti on H an dl er s ..................................................................................................... 10 6 2. 5. 4 V ect or T a bl e ................................................................................................................ 10 6 2. 5. 5 Ex ce pti on P ri or it ie s ...................................................................................................... 107 2. 5. 6 In te rru pt P ri ori ty G rou pi ng ............................................................................................ 108 2. 5. 7 Ex ce pti on E nt ry a nd R etu rn ......................................................................................... 10 8 2. 6 Fa ul t Han dl in g ............................................................................................................. 111 2. 6. 1 Fa ul t T y pe s ................................................................................................................. 112 2. 6. 2 Fa ul t Esc al at io n an d Har d Fa ult s .................................................................................. 1 12 2.6.3 Fault Status Registers and Fault Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2. 6. 4 Lo ck up ....................................................................................................................... 113 2. 7 Po we r Man ag em en t .................................................................................................... 114 2. 7. 1 En te rin g Sl ee p Mo de s ................................................................................................. 114 2. 7. 2 W a ke U p fr om S le ep M od e .......................................................................................... 114 2. 8 In st ruc ti on S et S um mar y .............................................................................................. 1 15 3 Cortex-M4 Peripherals ......................................................................................... 122 3. 1 Fu nc tio na l De sc ri pt io n ................................................................................................. 12 2 3. 1. 1 Sy st em T i mer ( Sy sT i ck) ............................................................................................... 12 3 3. 1. 2 Ne st ed V ec to re d Int er ru pt C on tr ol le r (N VI C) .................................................................. 12 4 3. 1. 3 Sy st em Co nt ro l Bl oc k (SC B) ........................................................................................ 12 5 3. 1. 4 Me mo ry Pr ot ec ti on U ni t (M PU ) ..................................................................................... 12 5 3. 1. 5 Fl oa tin g- Po in t Un it (F PU ) ............................................................................................. 130 3. 2 Re gi ste r Ma p .............................................................................................................. 13 4 3. 3 Sy st em T i mer ( Sy sT i ck) R eg ist er D es cr ip ti on s .............................................................. 1 37 3. 4 NV IC R eg is te r Des cr ip ti on s .......................................................................................... 14 1 3. 5 Sy st em C on tr ol Bl oc k (S CB ) Re gi st er D esc ri pt io ns ........................................................ 15 6 3.6 Memory Protection Unit (MPU) Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 3. 7 Fl oa tin g- Po in t Un it ( FPU ) Re gis te r De sc ri pti on s ............................................................ 1 94 4 JT AG Interface ...................................................................................................... 200 4. 1 Bl oc k Dia gr am ............................................................................................................ 20 1 4. 2 Si gn al De sc ri pt io n ....................................................................................................... 20 1 4. 3 Fu nc tio na l De sc ri pt io n ................................................................................................. 20 2 4. 3. 1 JT AG In te rfa ce P in s ..................................................................................................... 20 2 4. 3. 2 JT AG T AP C on tro ll er ................................................................................................... 204 4. 3. 3 Sh if t Reg is te rs ............................................................................................................ 20 4 4. 3. 4 Op er ati on al C on si de ra ti ons .......................................................................................... 20 5 4. 4 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 207 4. 5 Re gi ste r De sc ri pt io ns .................................................................................................. 20 8 4. 5. 1 In st ruc ti on R egi st er (I R) ............................................................................................... 20 8 4. 5. 2 Da ta R egi st er s ............................................................................................................ 210 5 System Control ..................................................................................................... 212 5. 1 Si gn al De sc ri pt io n ....................................................................................................... 21 2 5. 2 Fu nc tio na l De sc ri pt io n ................................................................................................. 21 2 5. 2. 1 De vi ce Id en tif ic at io n .................................................................................................... 21 2 5. 2. 2 Re se t Con tr ol .............................................................................................................. 21 3 5. 2. 3 No n- Mas ka bl e In te rru pt ............................................................................................... 21 8 5. 2. 4 Po we r Con tr ol ............................................................................................................. 21 8 5. 2. 5 Cl oc k Con tr ol .............................................................................................................. 21 9 June 12, 2014 4 T exas Instruments-Production Data T able of Contents 5. 2. 6 Sy st em Co nt ro l ........................................................................................................... 227 5. 3 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 231 5. 4 Re gi ste r Ma p .............................................................................................................. 23 1 5. 5 Sy st em C on tr ol Re gi st er D es cr ip ti ons ........................................................................... 23 7 5. 6 Sy st em C on tr ol Le ga cy R eg is ter D es cr ip ti ons ............................................................... 42 4 6 System Exception Module ................................................................................... 485 6. 1 Fu nc tio na l De sc ri pt io n ................................................................................................. 48 5 6. 2 Re gi ste r Ma p .............................................................................................................. 48 5 6. 3 Re gi ste r De sc ri pt io ns .................................................................................................. 48 5 7 Hibernation Module .............................................................................................. 493 7. 1 Bl oc k Dia gr am ............................................................................................................ 49 4 7. 2 Si gn al De sc ri pt io n ....................................................................................................... 49 4 7. 3 Fu nc tio na l De sc ri pt io n ................................................................................................. 49 5 7. 3. 1 Re gi ste r Ac ce ss T im in g ............................................................................................... 49 5 7. 3. 2 Hi be rna ti on C lo ck S our ce ............................................................................................ 49 6 7. 3. 3 Sy st em Im pl em en ta tio n ............................................................................................... 497 7. 3. 4 Ba tt ery M an ag em en t ................................................................................................... 498 7. 3. 5 Re al -T i me Cl oc k .......................................................................................................... 49 9 7. 3. 6 Ba tt ery -B ac ke d Me mo ry .............................................................................................. 50 1 7. 3. 7 Po we r Con tr ol U si ng H IB ............................................................................................. 50 1 7. 3. 8 Po we r Con tr ol U si ng V DD3 ON M od e ........................................................................... 501 7. 3. 9 In it iat in g Hi be rn at e ...................................................................................................... 501 7. 3. 10 W a ki ng f ro m Hi be rna te ................................................................................................ 50 1 7. 3. 1 1 Ar bi tra ry P ow er R em ova l ............................................................................................. 5 02 7. 3. 12 In te rru pt s an d St at us ................................................................................................... 502 7. 4 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 503 7. 4. 1 In it ial iz at io n ................................................................................................................. 50 3 7. 4. 2 R TC M atc h Fu nct io na li ty ( No H ib er nat io n) .................................................................... 50 4 7. 4. 3 R TC M atc h/ W ak e-U p fr om Hi be rn at io n ......................................................................... 5 04 7. 4. 4 Ex te rna l W ak e- Up fr om H ib er na ti on .............................................................................. 50 4 7. 4. 5 R TC o r Ext er nal W ak e-U p fr om Hi be rna ti on .................................................................. 50 5 7. 5 Re gi ste r Ma p .............................................................................................................. 50 5 7. 6 Re gi ste r De sc ri pt io ns .................................................................................................. 50 6 8 Internal Memory ................................................................................................... 524 8. 1 Bl oc k Dia gr am ............................................................................................................ 52 4 8. 2 Fu nc tio na l De sc ri pt io n ................................................................................................. 52 5 8. 2. 1 SR AM ........................................................................................................................ 52 5 8. 2. 2 RO M .......................................................................................................................... 52 6 8. 2. 3 Fl as h Mem or y ............................................................................................................. 52 8 8. 2. 4 EE PR OM .................................................................................................................... 534 8. 3 Re gi ste r Ma p .............................................................................................................. 54 0 8.4 Flash Memory Register Descriptions (Flash Control Offset) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 8. 5 EE PR OM Re gi st er D es cri pt io ns ( EE PRO M Of fs et ) ........................................................ 55 9 8.6 Memory Register Descriptions (System Control Offset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 9 Micro Direct Memory Access (\u03bcDMA) ................................................................ 585 9. 1 Bl oc k Dia gr am ............................................................................................................ 58 6 9. 2 Fu nc tio na l De sc ri pt io n ................................................................................................. 58 6 5 June 12, 2014 T exas Instruments-Production Data Tiva \u2122 TM4C123GH6PM Microcontroller 9. 2. 1 Ch an nel A ss ig nm en ts .................................................................................................. 587 9. 2. 2 Pr io rit y ........................................................................................................................ 58 8 9. 2. 3 Ar bi tra ti on S iz e ............................................................................................................ 588 9. 2. 4 Re qu est T y pe s ............................................................................................................ 588 9. 2. 5 Ch an nel C on fi gu ra tio n ................................................................................................. 5 89 9. 2. 6 T r an sf er M od es ........................................................................................................... 59 1 9. 2. 7 T r an sf er S iz e an d Inc re me nt ........................................................................................ 59 9 9. 2. 8 Pe ri phe ra l In te rf ace ..................................................................................................... 59 9 9. 2. 9 So ft war e Re qu es t ........................................................................................................ 59 9 9. 2. 10 In te rru pt s an d Er ro rs .................................................................................................... 60 0 9. 3 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 600 9. 3. 1 Mo du le In it ial iz at io n ..................................................................................................... 60 0 9. 3. 2 Co nf igu ri ng a M em or y-t o- Me mo ry T r an sfe r ................................................................... 60 1 9. 3. 3 Co nf igu ri ng a P er ip her al f or S im pl e T ra nsm it ................................................................ 60 2 9. 3. 4 Co nf igu ri ng a P er ip her al f or P in g- Po ng R ec ei ve ............................................................ 60 4 9. 3. 5 Co nf igu ri ng C ha nn el As si gn me nt s ................................................................................ 60 6 9. 4 Re gi ste r Ma p .............................................................................................................. 60 6 9. 5 \u03bcD MA C han ne l Co nt ro l Str uc tu re ................................................................................. 60 8 9. 6 \u03bcD MA R egi st er D es cr ip ti on s ........................................................................................ 61 5 10 General-Purpose Input/Outputs (GPIOs) ........................................................... 649 10 .1 Si gn al De sc ri pt io n ....................................................................................................... 64 9 10 .2 Fu nc tio na l De sc ri pt io n ................................................................................................. 65 2 10 .2 .1 Da ta C ont ro l ............................................................................................................... 65 3 10 .2 .2 In te rru pt C on tr ol .......................................................................................................... 65 4 10 .2 .3 Mo de C ont ro l .............................................................................................................. 65 5 10 .2 .4 Co mm it Co nt ro l ........................................................................................................... 656 10 .2 .5 Pa d Co ntr ol ................................................................................................................. 65 6 10 .2 .6 Id en tif ic at io n ............................................................................................................... 656 10 .3 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 656 10 .4 Re gi ste r Ma p .............................................................................................................. 65 8 10 .5 Re gi ste r De sc ri pt io ns .................................................................................................. 66 1 1 1 General-Purpose Timers ...................................................................................... 704 1 1. 1 Bl oc k Dia gr am ............................................................................................................ 70 5 1 1. 2 Si gn al De sc ri pt io n ....................................................................................................... 70 6 1 1. 3 Fu nc tio na l De sc ri pt io n ................................................................................................. 70 7 1 1. 3. 1 GP TM R es et C on di ti on s .............................................................................................. 70 8 1 1. 3. 2 T i me r Mo de s ............................................................................................................... 709 1 1. 3. 3 W a it -f or -T ri gge r Mo de .................................................................................................. 718 1 1. 3. 4 Sy nc hro ni zi ng G P T im er B loc ks ................................................................................... 71 9 1 1. 3. 5 DM A Op era ti on ........................................................................................................... 720 1 1.3.6 Accessing Concatenated 16/32-Bit GPTM Register V alues .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 1 1.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register V alues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 1 1. 4 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 722 1 1. 4. 1 On e- Sho t/ Pe ri od ic T i me r Mo de .................................................................................... 72 2 1 1. 4. 2 Re al -T i me Cl oc k (R TC ) Mod e ...................................................................................... 72 3 1 1. 4. 3 In pu t Edg e- Co un t Mo de ............................................................................................... 723 1 1. 4. 4 In pu t Ed ge T im e Mo de ................................................................................................. 72 4 1 1. 4. 5 PW M Mo de ................................................................................................................. 724 June 12, 2014 6 T exas Instruments-Production Data T able of Contents 1 1. 5 Re gi ste r Ma p .............................................................................................................. 72 5 1 1. 6 Re gi ste r De sc ri pt io ns .................................................................................................. 72 6 12 W atchdog T imers ................................................................................................. 774 12 .1 Bl oc k Dia gr am ............................................................................................................ 77 5 12 .2 Fu nc tio na l De sc ri pt io n ................................................................................................. 77 5 12 .2 .1 Re gi ste r Ac ce ss T im in g ............................................................................................... 77 6 12 .3 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 776 12 .4 Re gi ste r Ma p .............................................................................................................. 77 6 12 .5 Re gi ste r De sc ri pt io ns .................................................................................................. 77 7 13 Analog-to-Digital Converter (ADC) ..................................................................... 799 13 .1 Bl oc k Dia gr am ............................................................................................................ 80 0 13 .2 Si gn al De sc ri pt io n ....................................................................................................... 80 1 13 .3 Fu nc tio na l De sc ri pt io n ................................................................................................. 80 2 13 .3 .1 Sa mp le Se qu en ce rs .................................................................................................... 80 2 13 .3 .2 Mo du le Co nt ro l ............................................................................................................ 803 13 .3 .3 Ha rd war e Sa mp le A v era gi ng Ci rc ui t ............................................................................. 807 13 .3 .4 An al og- to -D ig it al C on ve rte r .......................................................................................... 8 07 13 .3 .5 Di f fer en tia l Sa mp li ng ................................................................................................... 81 0 13 .3 .6 In te rna l T em per at ure S en so r ........................................................................................ 812 13 .3 .7 Di gi tal C om pa ra to r Un it ............................................................................................... 81 3 13 .4 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 817 13 .4 .1 Mo du le In it ial iz at io n ..................................................................................................... 81 7 13 .4 .2 Sa mp le Se qu en ce r Co nf ig ur ati on ................................................................................. 81 8 13 .5 Re gi ste r Ma p .............................................................................................................. 81 8 13 .6 Re gi ste r De sc ri pt io ns .................................................................................................. 82 0 14 Universal Asynchronous Receivers/T ransmitters (UART s) ............................. 893 14 .1 Bl oc k Dia gr am ............................................................................................................ 89 4 14 .2 Si gn al De sc ri pt io n ....................................................................................................... 89 4 14 .3 Fu nc tio na l De sc ri pt io n ................................................................................................. 89 5 14 .3 .1 T r an sm it /R ec eiv e Lo gi c ............................................................................................... 895 14 .3 .2 Ba ud -Ra te G en er at io n ................................................................................................. 896 14 .3 .3 Da ta T r an smi ss ion ...................................................................................................... 89 7 14 .3 .4 Se ri al IR ( SI R) ............................................................................................................. 89 7 14 .3 .5 IS O 78 16 Su pp ort ....................................................................................................... 89 8 14 .3 .6 Mo de m Han ds ha ke S up po rt ......................................................................................... 89 9 14 .3 .7 9- Bi t UAR T M ode ........................................................................................................ 90 0 14 .3 .8 FI FO O per at io n ........................................................................................................... 900 14 .3 .9 In te rru pt s .................................................................................................................... 90 0 14 .3 .10 L oo pb ac k Ope ra ti on .................................................................................................... 90 1 14 .3 .1 1 DM A Op er at io n ........................................................................................................... 902 14 .4 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 902 14 .5 Re gi ste r Ma p .............................................................................................................. 90 3 14 .6 Re gi ste r De sc ri pt io ns .................................................................................................. 90 5 15 Synchronous Serial Interface (SSI) .................................................................... 952 15 .1 Bl oc k Dia gr am ............................................................................................................ 95 3 15 .2 Si gn al De sc ri pt io n ....................................................................................................... 95 3 15 .3 Fu nc tio na l De sc ri pt io n ................................................................................................. 95 4 7 June 12, 2014 T exas Instruments-Production Data Tiva \u2122 TM4C123GH6PM Microcontroller 15 .3 .1 Bi t Ra te Ge ne ra ti on ..................................................................................................... 95 4 15 .3 .2 FI FO O per at io n ........................................................................................................... 955 15 .3 .3 In te rru pt s .................................................................................................................... 95 5 15 .3 .4 Fr am e For ma ts ........................................................................................................... 956 15 .3 .5 DM A Op era ti on ........................................................................................................... 964 15 .4 In it ial iz at io n an d Con fi gu ra ti on ..................................................................................... 965 15 .5 Re gi ste r Ma p .............................................................................................................. 96 7 15 .6 Re gi ste r De sc ri pt io ns .................................................................................................. 96 8 16 Inter-Integrated Circuit (I 2 C) Interface ................................................................ 997 16 .1 Bl oc k Dia gr am ............................................................................................................ 99 8 16 .2 Si gn al De sc ri pt io n ....................................................................................................... 99 8 16 .3 Fu nc tio na l De sc ri pt io n ................................................................................................. 99 9 16.3.1 I 2 C Bu s Fu nc ti on al Ov er vi ew ........................................................................................ 99 9 16 .3 .2 A va ila bl e Spe ed M od es ............................................................................................. 10 03 16 .3 .3 In te rru pt s .................................................................................................................. 1 005 16 .3 .4 Lo op bac k Op er at io n .................................................................................................. 10 06 16 .3 .5 Co mm and S eq ue nc e Fl ow Ch ar ts .............................................................................. 10 07 16 .4 In it ial iz at io n an d Con fi gu ra ti on .................................................................................... 101 5 16.4.1 Configure the I 2 C Module to T ransmit a Single Byte as a Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 16.4.2 Configure the I 2 C Mas te r to Hi gh S pee d Mo de ............................................................ 10 16 16 .5 Re gi ste r Ma p ............................................................................................................ 101 7 16.6 Register Descriptions (I 2 C Ma st er ) .............................................................................. 101 8 16.7 Register Descriptions (I 2 C Sl av e) ............................................................................... 103 5 16.8 Register Descriptions (I 2 C St at us a nd Co nt rol ) ............................................................ 10 45 17 Controller Area Network (CAN) Module ........................................................... 1048 17 .1 Bl oc k Dia gr am ........................................................................................................... 10 49 17 .2 Si gn al De sc ri pt io n ..................................................................................................... 10 49 17 .3 Fu nc tio na l De sc ri pt io n ............................................................................................... 10 50 17 .3 .1 In it ial iz at io n ............................................................................................................... 1 05 1 17 .3 .2 Op er ati on .................................................................................................................. 10 51 17 .3 .3 T r an sm it ti ng M ess ag e Ob je ct s ................................................................................... 105 2 17 .3 .4 Co nf igu ri ng a T r ans mi t Me ss ag e Obj ec t ...................................................................... 10 53 17 .3 .5 Up da tin g a T ra ns mit M es sa ge O bj ect ......................................................................... 10 54 17 .3 .6 Ac ce pti ng R ec ei ve d Mes sa ge Ob je ct s ........................................................................ 105 4 17 .3 .7 Re ce ivi ng a D at a Fr am e ............................................................................................ 10 55 17 .3 .8 Re ce ivi ng a R em ot e Fr ame ........................................................................................ 10 55 17 .3 .9 Re ce ive /T ran sm it Pr io ri ty ........................................................................................... 10 56 17 .3 .10 Co nf igu ri ng a R ec ei ve M es sa ge O bj ec t ...................................................................... 10 56 17 .3 .1 1 Ha ndl in g of Re ce iv ed M es sa ge O bj ect s ...................................................................... 10 57 17 .3 .12 H an dl in g o f In te rru pt s ................................................................................................ 10 59 17 .3 .13 T e st Mo de ................................................................................................................. 10 60 17 .3 .14 Bi t T im in g Con fi gur at io n Er ro r Con si de ra ti ons ............................................................. 10 62 17 .3 .15 Bi t T im e an d B it R at e ................................................................................................. 10 62 17 .3 .16 Ca lc ula ti ng t he B it T i mi ng Pa ra met er s ........................................................................ 10 64 17 .4 Re gi ste r Ma p ............................................................................................................ 106 7 17 .5 CA N Re gis te r De sc ri pt io ns ......................................................................................... 10 68 June 12, 2014 8 T exas Instruments-Production Data T able of Contents 18 Universal Serial Bus (USB) Controller ............................................................. 1099 18 .1 Bl oc k Dia gr am ........................................................................................................... 11 00 18 .2 Si gn al De sc ri pt io n ..................................................................................................... 11 00 18 .3 Fu nc tio na l De sc ri pt io n ............................................................................................... 11 01 18 .3 .1 Op er ati on a s a De vic e ............................................................................................... 1 10 1 18 .3 .2 Op er ati on a s a Ho st ................................................................................................... 110 7 18 .3 .3 OT G Mo de ................................................................................................................ 11 10 18 .3 .4 DM A Op era ti on ......................................................................................................... 111 2 18 .4 In it ial iz at io n an d Con fi gu ra ti on .................................................................................... 111 3 18 .4 .1 Pi n Co nfi gu ra ti on ....................................................................................................... 11 13 18 .4 .2 En dp oin t Co nf ig ur at io n .............................................................................................. 11 14 18 .5 Re gi ste r Ma p ............................................................................................................ 111 4 18 .6 Re gi ste r De sc ri pt io ns ................................................................................................. 11 20 19 Analog Comparators .......................................................................................... 1215 19 .1 Bl oc k Dia gr am ........................................................................................................... 12 16 19 .2 Si gn al De sc ri pt io n ..................................................................................................... 12 16 19 .3 Fu nc tio na l De sc ri pt io n ............................................................................................... 12 17 19 .3 .1 In te rna l Re fe re nc e Pr og ra mm in g ................................................................................ 12 18 19 .4 In it ial iz at io n an d Con fi gu ra ti on .................................................................................... 122 0 19 .5 Re gi ste r Ma p ............................................................................................................ 122 0 19 .6 Re gi ste r De sc ri pt io ns ................................................................................................. 12 21 20 Pulse Width Modulator (PWM) .......................................................................... 1230 20 .1 Bl oc k Dia gr am ........................................................................................................... 12 31 20 .2 Si gn al De sc ri pt io n ..................................................................................................... 12 33 20 .3 Fu nc tio na l De sc ri pt io n ............................................................................................... 12 34 20 .3 .1 Cl oc k Con fi gu ra ti on ................................................................................................... 123 4 20 .3 .2 PW M T im er ............................................................................................................... 12 34 20 .3 .3 PW M Co mpa ra to rs .................................................................................................... 12 34 20 .3 .4 PW M Si gna l Ge ne ra to r .............................................................................................. 1 23 5 20 .3 .5 De ad -Ba nd G en er at or ............................................................................................... 123 6 20 .3 .6 In te rru pt /A DC -T rig ge r Sel ec to r ................................................................................... 123 6 20 .3 .7 Sy nc hro ni za ti on M et ho ds .......................................................................................... 123 7 20 .3 .8 Fa ul t Con di ti on s ........................................................................................................ 12 38 20 .3 .9 Ou tp ut C on tr ol B lo ck .................................................................................................. 12 39 20 .4 In it ial iz at io n an d Con fi gu ra ti on .................................................................................... 123 9 20 .5 Re gi ste r Ma p ............................................................................................................ 124 0 20 .6 Re gi ste r De sc ri pt io ns ................................................................................................. 12 43 21 Quadrature Encoder Interface (QEI) ................................................................. 1305 21 .1 Bl oc k Dia gr am ........................................................................................................... 13 05 21 .2 Si gn al De sc ri pt io n ..................................................................................................... 13 07 21 .3 Fu nc tio na l De sc ri pt io n ............................................................................................... 13 08 21 .4 In it ial iz at io n an d Con fi gu ra ti on .................................................................................... 131 0 21 .5 Re gi ste r Ma p ............................................................................................................ 131 0 21 .6 Re gi ste r De sc ri pt io ns ................................................................................................. 13 11 22 Pin Diagram ........................................................................................................ 1328 23 Signal T ables ...................................................................................................... 1329 23 .1 Si gn als b y Pi n Nu mb er .............................................................................................. 13 30 9 June 12, 2014 T exas Instruments-Production Data Tiva \u2122 TM4C123GH6PM Microcontroller 23 .2 Si gn als b y Si gn al N am e ............................................................................................. 13 37 23 .3 Si gn als b y Fu nc ti on , Ex ce pt f or G PI O ......................................................................... 13 44 23 .4 GP IO P ins a nd A lte rn ate F un ct io ns ............................................................................ 13 51 23 .5 Po ss ibl e Pi n As si gn me nt s fo r Al te rn ate Fu nc tio ns ....................................................... 13 53 23 .6 Co nn ect io ns f or U nu se d Si gn als ................................................................................. 13 56 24 Electrical Characteristics .................................................................................. 1358 24 .1 Ma xi mum R at in gs ...................................................................................................... 13 58 24 .2 Op er ati ng C ha ra ct er is ti cs ........................................................................................... 135 9 24 .3 Re co mme nd ed O pe ra tin g Co nd it io ns ......................................................................... 136 0 24 .4 Lo ad C ond it io ns ........................................................................................................ 13 62 24 .5 JT AG an d Bo und ar y Sc an .......................................................................................... 13 63 24 .6 Po we r and B ro wn- Ou t ............................................................................................... 13 65 24 .6 .1 VD DA L eve ls ............................................................................................................ 13 65 24 .6 .2 VD D Le vel s ............................................................................................................... 13 66 24 .6 .3 VD DC L eve ls ............................................................................................................ 13 67 24 .6 .4 VD D Gl itc he s ............................................................................................................ 13 68 24 .6 .5 VD D Dr oo p Re sp ons e ............................................................................................... 13 68 24 .7 Re se t ........................................................................................................................ 13 70 24 .8 On -C hip L ow D ro p- Ou t (L DO ) Re gu la to r ..................................................................... 13 73 24 .9 Cl oc ks ...................................................................................................................... 137 4 24 .9 .1 PL L Sp eci fi ca ti on s ..................................................................................................... 1 374 24 .9 .2 PI OS C Spe ci fi ca ti on s ................................................................................................ 13 75 24.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 24 .9 .4 Hi be rna ti on C lo ck S our ce S pe ci fi ca ti on s ..................................................................... 137 5 24 .9 .5 Ma in O sci ll at or S pe cif ic at io ns ..................................................................................... 13 76 24 .9 .6 Sy st em Cl oc k Sp ec if ica ti on w it h AD C Ope ra ti on .......................................................... 13 80 24 .9 .7 Sy st em Cl oc k Sp ec if ica ti on w it h US B Ope ra ti on .......................................................... 13 80 24 .1 0 Sl ee p Mod es ............................................................................................................. 13 81 24 .1 1 Hi be rna ti on M od ul e ................................................................................................... 13 83 24 .1 2 Fl as h Me mo ry a nd EE PR OM ..................................................................................... 13 84 24 .1 3 In pu t/O ut pu t Pi n Ch ara ct eri st ic s ................................................................................. 1 38 5 24 .1 3.1 G PI O Mo dul e Ch ar act er ist ic s ..................................................................................... 1 38 5 24 .1 3.2 T ype s of I /O Pi ns a nd ES D Pr ote ct ion ......................................................................... 13 85 24 .1 4 An al og- to -D ig it al C on ve rt er ( AD C) .............................................................................. 138 9 24 .1 5 Sy nc hro no us S er ia l Int er fac e (S SI ) ............................................................................. 139 2 24.16 Inter-Integrated Circuit (I 2 C) I nt er fa ce ......................................................................... 139 5 24 .1 7 Un iv ers al S er ia l Bu s (U SB ) Co nt ro ll er ......................................................................... 139 6 24 .1 8 An al og Co mp ar at or ................................................................................................... 13 97 24 .1 9 Pu ls e-W id th M od ul at or ( PW M) ................................................................................... 1 39 8 24 .2 0 Cu rr ent C on su mp ti on ................................................................................................. 139 9 A Package Information .......................................................................................... 1402 A. 1 Or de rab le D ev ic es ..................................................................................................... 14 02 A. 2 De vi ce No me nc la tu re ................................................................................................ 140 2 A. 3 De vi ce Ma rk in gs ........................................................................................................ 14 03 A. 4 Pa ck agi ng D ia gr am ................................................................................................... 14 04 June 12, 2014 10 T exas Instruments-Production Data T able of Contents

M 03 - DataSheet - TM4C123GH6PM

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